High performance symmetric multiprocessing systems via super-coherent data mechanisms

• US 20030097529A1
• Filed: 10/16/2001
• Published: 05/22/2003
• Est. Priority Date: 10/16/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William J., Williams, Derek Edward, Arimilli, Ravi Kumar, Guthrie, Guy Lynn
• Granted Patent: US 6,785,774 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.

Claims

1. A method for improving performance of a multiprocessor data processing system comprising:

responsive to a receipt of a first system bus response to a coherency operation, executing operations on a processing unit of said multiprocessor data processing system utilizing super-coherent data; and

enabling coherent operations with other processing units responsive to an occurrence of a pre-determined condition.

2. The method of claim 1, said executing step further comprising:

first switching a first coherency state of a cache line providing said super-coherent data to a second cache coherency state that signals said processing unit to utilize said super-coherent data

3. The method of claim 2, further comprising:

enabling coherency state transitions to said second coherency state via coherency protocols.

4. The method of claim 3, further comprising:

issuing a request for data of said cache line to a system bus of said data processing system only when said cache line is not in said second coherency state.

5. The method of claim 4, wherein said enabling step includes transitioning from said second coherency state to a next coherency state when said predetermined condition occurs.

6. A system for improving performance of a multiprocessor data processing system comprising:

processor means, responsive to a receipt of a first system bus response to a coherency operation, for executing operations on a processing unit of said multiprocessor data processing system utilizing super-coherent data; and

logic for enabling coherent operations with other processing units responsive to an occurrence of a pre-determined condition.

7. The system of claim 6, further comprising:

control logic for first switching a first coherency state of a cache line providing said super-coherent data to a second cache coherency state that signals said processing unit to utilize said super-coherent data

8. The system of claim 7, further comprising:

means for enabling coherency state transitions to said second coherency state via coherency protocols.

9. The system of claim 8, further comprising:

means for issuing a request for data of said cache line to a system bus of said data processing system only when said cache line is not in said second coherency state.

10. The system of claim 9, further including means for transitioning from said second coherency state to a next coherency state when said predetermined condition occurs.

11. A multiprocessor data processing system comprising:

a plurality of processing units including a first processing unit;

a memory hierarchy including a plurality of caches, wherein each cache is affiliated with one of said plurality of processing units;

coupling means for interconnecting said plurality of processing units;

processing logic, responsive to a receipt of a first system bus response to a coherency operation, for executing operations on a processing unit of said multiprocessor data processing system utilizing super-coherent data; and

means for enabling coherent operations with other processing units responsive to an occurrence of a pre-determined condition.

12. The data processing system of claim 11, further comprising:

means for first switching a first coherency state of a cache line providing said super-coherent data to a second cache coherency state that signals said processing unit to utilize said super-coherent data

13. The data processing system of claim 12, further comprising:

means for enabling coherency state transitions to said second coherency state via coherency protocols.

14. The data processing system of claim 13, further comprising:

means for issuing a request for data of said cache line to a system bus of said data processing system only when said cache line is not in said second coherency state.

15. The data processing system of claim 14, further comprising means for transitioning from said second coherency state to a next coherency state when said predetermined condition occurs.

16. A method for improving coherency operations within a multiprocessor data processing system comprising:

setting a cache line of a first processor to a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of said data processing system;

issuing a request for said cache line as a Z1 read on a system bus, responsive to said cache line being in said first coherency state;

responsive to an indication that said first processor should utilize data currently available within said cache line, changing said first coherency state to a second coherency state that indicates to said first processor that subsequent request by for said cache line should utilize the data within the cache and not be sent to said system bus; and

responding to said request with data of said cache line when said cache line indicates said second coherency state.

17. The method of claim 16, further comprising:

responsive to a subsequent request for said cache line when said cache line is in said second coherency state, immediately providing said data of said cache line to said processor.

18. The method of claim 17, further comprising:

monitoring a response to said request; and

when said response indicates that said first processor should utilize new data and that a lock has been acquired for the cache line,

retrying said Z1 read until said shared cache line is provided to said first processor from said second processor; and

changing said first coherency state to a fourth coherency state when said data is provided to said first processor.

19. The method of claim 17, further comprising:

responsive to a receipt of a predetermined condition, changing said first and second coherency state to a third coherency state that indicates that said cache line is not valid.

20. The method of claim 19, wherein said data processing system comprises a main cache directory, a sub-directory for storing cache line addresses for cache lines in said first and second cache coherency states, and a clear on barrier flag (COBF) associated with said sub-directory, said method further comprising:

setting said COBF whenever an operation of said first processor is issued to said system bus; and

responsive to a receipt of a barrier instruction at said first processor when said COBF is set, dynamically flushing all contents of said sub-directory.

21. The method of claim 20, wherein said dynamic flushing comprises invalidating each entry within said sub-directory.

22. The method of claim 17, further comprising:

responsive to a receipt of one of a plurality of first operations by said first processor, changing said second coherency state back to said first coherency state, wherein said plurality of first operations includes a snooped DClaim and a snooped RWITM.

23. The method of claim 17, further comprising:

responsive to a snoop of a second operation by said first processor, changing said second coherency state to a fourth coherency state, wherein said second operation includes a bus RWITM, and said fourth coherency state indicates that said cache line is modified.

24. The method of claim 17, further comprising:

responsive to a snoop of a third operation by said first processor, changing said first coherency state to a fifth coherency state, wherein said third operation includes a bus read with a null response, and said fourth coherency state indicates that said cache line is exclusive.

25. The method of claim 17, further comprising:

responsive to a snoop of a fourth operation by said first processor, changing said first coherency state to a sixth coherency state, wherein said fourth operation includes a bus read with shared response and a bus read with modified, use new data response and said sixth coherency state indicates that said cache line is shared.

26. The method of claim 17, further comprising:

responsive to a snoop of a fourth operation by said first processor, changing said first coherency state to a modified coherency state, wherein said fourth operation includes a bus RWITM.

27. A multiprocessor data processing system comprising:

a plurality of processors each having a cache that supports coherency operations;

a system bus interconnecting said plurality of cache lines; and

operational logic that provides;

means for setting a cache line of a first processor to a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of said data processing system;

means for issuing a request for said cache line as a Z1 read on a system bus, responsive to said cache line being in said first coherency state;

means responsive to an indication that said first processor should utilize data currently available within said cache line, for changing said first coherency state to a second coherency state that indicates to said first processor that subsequent request for said cache line should utilize the data within the cache and not be sent to said system bus; and

means for responding to said request with data of said cache line when said cache line indicates said second coherency state.

28. The data processing system of claim 27, further comprising:

means, responsive to a subsequent request for said cache line when said cache line is in said second coherency state, for immediately providing said data of said cache line to said processor.

29. The data processing system of claim 28, further comprising:

means for monitoring a response to said request; and

means, when said response indicates that said first processor should utilize new data and that a lock has been acquired for the cache line, for;

retrying said Z1 read until said shared cache line is provided to said first processor from said second processor; and

changing said first coherency state to a fourth coherency state when said data is provided to said first processor.

30. The data processing system of claim 28, further comprising:

a cache coherency protocol that includes said first coherency state and said second coherency state and transition guidelines for enabling coherency operations while utilizing super-coherent data.

31. The data processing system of claim 30, further comprising:

a main cache directory; and

a sub-directory for storing cache line addresses for cache lines in said first and second cache coherency states.

32. The data processing system of claim 31, further comprising:

a clear on barrier flag (COBF) associated with said sub-directory; and

logic for (1) setting said COBF whenever an operation of said first processor is issued to said system bus, and (2) responsive to a receipt of a barrier instruction at said first processor when said COBF is set, dynamically flushing all contents of said sub-directory.