Error detection on programmable logic resources
First Claim
1. A circuit that detects errors in configuration data stored on a logic device, comprising:
- a memory in which the configuration data is stored; and
check circuitry coupled to the memory to analyze configuration data stored in the memory to determine if any values have changed after initial configuration of the memory.
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Accused Products
Abstract
Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
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Citations
81 Claims
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1. A circuit that detects errors in configuration data stored on a logic device, comprising:
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a memory in which the configuration data is stored; and
check circuitry coupled to the memory to analyze configuration data stored in the memory to determine if any values have changed after initial configuration of the memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An error detection circuit implemented on a logic device, comprising:
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a multiplexer that takes as input an expected value and configuration data stored on the logic device; and
check circuitry coupled to an output of the multiplexer that includes;
an XOR tree to implement a polynomial checksum computation, a signature register coupled to the XOR tree, and a logic gate coupled to the signature register, wherein the logic gate takes, as a bit-wise input, content of the signature register. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A method for detecting errors in configuration data programmed into a logic device, comprising:
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computing an expected value based on the configuration data that is programmed onto the logic device;
analyzing configuration data stored on the logic device to determine if an error has occurred. - View Dependent Claims (46, 47, 48, 49, 50, 51)
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52. Circuitry for accessing configuration data stored on a logic device and sending the configuration data to an output, comprising:
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a memory in which the configuration data is stored, wherein the memory comprises frames of memory cells;
an address register capable of storing a number of bits at least equal to a number of the frames, wherein each bit stored in the address register is associated with a different frame of the frames of memory cells;
a data register coupled to the memory; and
control logic coupled to the memory, the address register, and the data register to access a particular frame of memory cells, wherein the control logic asserts a bit in the address register associated with the particular frame of memory cells, causes data from the particular frame of memory cells to be loaded into the data register, and causes a subset of data from the particular frame of memory cells to be loaded from the data register to the output. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
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65. Control logic that controls the communication of configuration data stored in a memory to an output circuitry, wherein the memory comprises frames of memory cells, the control logic being coupled to:
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the memory;
an address register in which each bit location is associated with a distinct frame of the frames of memory cells; and
a data register that is further coupled to the memory, wherein the control logic;
a. asserts a bit in the address register to indicate a selection of a particular frame of memory cells, b. loads the particular frame of memory cells to the data register, c. loads the particular frame of memory cells in the data register to the output circuitry, wherein the particular frame of memory cells is loaded to the output circuitry one portion per clock cycle at a time, and d. repeats a-c for each frame of the frames of memory cells. - View Dependent Claims (66, 67, 68, 69, 70, 71, 72)
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73. A method for accessing configuration data stored on a logic device and sending the configuration data to an output using control logic, comprising:
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asserting a bit in an address register associated with a particular frame of memory cells in a memory in which the configuration data is stored;
loading data from the particular frame of memory cells into a data register; and
loading a subset of the data from the particular frame of memory cells from the data register to the output. - View Dependent Claims (74, 75, 76, 77, 78, 79, 80, 81)
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Specification