Error detection on programmable logic resources

• US 20030097628A1
• Filed: 10/10/2002
• Published: 05/22/2003
• Est. Priority Date: 10/11/2001
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ngo, Ninh D., Lee, Andy L., Veenstra, Kerry
• Granted Patent: US 7,310,757 B2
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Claims

1. A circuit that detects errors in configuration data stored on a logic device, comprising:

a memory in which the configuration data is stored; and

check circuitry coupled to the memory to analyze configuration data stored in the memory to determine if any values have changed after initial configuration of the memory.

2. The logic device of claim 1 wherein the memory is random access memory.

3. The logic device of claim 1 wherein the check circuitry comprises:

checksum circuitry that computes a value based on the configuration data; and

comparison circuitry coupled to the checksum circuitry that compares the computed value to an expected value.

4. The logic device of claim 3 wherein the computed value is a remainder that results from dividing a value based on the configuration data by a predetermined value.

5. The logic device of claim 3 wherein the expected value is calculated from the configuration data used to configure the logic device.

6. The logic device of claim 5 wherein the expected value is calculated prior to configuring the logic device from a remainder that results from dividing a value based on the configuration data prior to being programmed onto the logic device by a predetermined value.

7. The logic device of claim 6 wherein the predetermined value is based on an equivalent value used by the checksum circuitry.

8. The logic device of claim 3 wherein the expected value is computed by the checksum circuitry while the configuration data is being programmed onto the logic device.

9. The logic device of claim 3 wherein the comparison circuitry provides one of:

a first signal indicating that no error was detected; and

a second signal indicating that an error was detected.

10. The logic device of claim 1 wherein the check circuitry comprises:

compute circuitry that computes a value based on the configuration data; and

logic circuitry coupled to the compute circuitry that performs a logical operation on the computed value.

11. The logic device of claim 10 wherein the computed value is a remainder that results from dividing a value based on the configuration data and an expected value by a predetermined value.

12. The logic device of claim 11 wherein the expected value is calculated from the configuration data used to configure the logic device.

13. The logic device of claim 12 wherein the expected value is calculated prior to configuring the logic device from a remainder that results from dividing a value based on the configuration data prior to being programmed onto the logic device by a predetermined value.

14. The logic device of claim 11 wherein the expected value is computed by the compute circuitry while the configuration data is being programmed onto the logic device.

15. The logic device of claim 10 wherein the logic circuitry comprises logic that generates one of:

a first signal indicating that no error was detected; and

a second signal indicating that an error was detected.

16. The logic device of claim 1 further comprising:

a second memory coupled to the memory, wherein the second memory stores a portion of the configuration data.

17. The logic device of claim 16 wherein the check circuitry is coupled to the second memory and performs part of the analysis on the portion of the configuration data.

18. The logic device of claim 1 further comprising:

a second memory used to store an expected value that is input to the check circuitry.

19. The logic device of claim 18 wherein the expected value is calculated from the configuration data used to configure the logic device.

20. The logic device of claim 19 wherein the expected value is calculated prior to configuring the logic device from a remainder that results from dividing a value based on the configuration data prior to being programmed onto the logic device by a predetermined value.

21. The logic device of claim 18 wherein the expected value is computed by the check circuitry while the configuration data is being programmed onto the logic device.

22. The logic device of claim 1 further comprising output circuitry coupled to the check circuitry to output a signal that indicates whether an error was detected.

23. A digital signal processing system comprising:

processing circuitry;

a second memory coupled to said processing circuitry; and

the logic device as defined in claim 1.

24. A printed circuit board on which is mounted the logic device as defined in claim 1.

25. The printed circuit board as defined in claim 24 further comprising:

a second memory mounted on the printed circuitry board and coupled to the logic device.

26. The printed circuit board defined in claim 25 wherein the second memory contains nonvolatile memory that stores the configuration data that is programmed into the logic device.

27. An error detection circuit implemented on a logic device, comprising:

a multiplexer that takes as input an expected value and configuration data stored on the logic device; and

check circuitry coupled to an output of the multiplexer that includes;

an XOR tree to implement a polynomial checksum computation,

a signature register coupled to the XOR tree, and

a logic gate coupled to the signature register, wherein the logic gate takes, as a bit-wise input, content of the signature register.

28. The error detection circuit of claim 27 further comprising a first memory in which the configuration data is stored.

29. The error detection circuit of claim 28 further comprising a second memory coupled to the first memory, wherein the second memory stores a portion of the configuration data to be sent as input to the multiplexer.

30. The error detection circuit of claim 27 further comprising a memory used to store the expected value.

31. The error detection circuit of claim 30 wherein the expected value is calculated from the configuration data used to configure the logic device.

32. The error detection circuit of claim 31 wherein the expected value is calculated prior to configuring the logic device from a remainder that results from dividing a value based on the configuration data prior to being programmed onto the logic device by a predetermined value.

33. The error detection circuit of claim 30 wherein the expected value is computed by the check circuitry while the configuration data is being programmed onto the logic device.

34. The error detection circuit of claim 27 wherein the multiplexer sends first as output the configuration data and sends second as output the expected value.

35. The error detection circuit of claim 27 wherein the XOR tree comprises registers for storing results of the polynomial checksum computation at each clock cycle and further sends the results as input to the XOR tree in a next clock cycle.

36. The error detection circuit of claim 35 wherein the results that are stored in the registers are sent to and stored in the signature register in the next clock cycle.

37. The error detection circuit of claim 27 wherein the XOR tree computes a remainder that results from dividing a value based on the configuration data and the expected value by a predetermined value.

38. The error detection circuit of claim 27 wherein the logic gate sends as output one of:

a first bit when the content of the signature register is a predetermined value; and

a second bit when the content of the signature register is other than the predetermined value.

39. The error detection circuit of claim 27 further comprising an output pin coupled to an output of the logic gate to output a signal that indicates whether an error was detected

40. The error detection circuit of claim 39 wherein the output pin is accessible by user logic.

41. The error detection circuit of claim 27 wherein the error detection circuit is a hard-wired circuit resident on the logic device.

42. The error detection circuit of claim 27 wherein the error detection circuit is programmed into the logic device.

43. The error detection circuit of claim 27 wherein the error detection circuit is external to the logic device and coupled to the logic device using input/output pins.

44. The error detection circuit of claim 27 wherein the error detection circuit is implemented in software.

45. A method for detecting errors in configuration data programmed into a logic device, comprising:

computing an expected value based on the configuration data that is programmed onto the logic device;

analyzing configuration data stored on the logic device to determine if an error has occurred.

46. The method of claim 45 wherein computing the expected value comprises calculating prior to configuring the logic device from a remainder that results from dividing a value based on the configuration data prior to being programmed onto the logic device by a predetermined value.

47. The method of claim 45 wherein computing the expected value comprises calculating while configuring the logic device from a remainder that results from dividing a value based on the configuration data while being programmed onto the logic device by a predetermined value.

48. The method of claim 45 wherein analyzing configuration data comprises:

computing a value based on the configuration data; and

comparing the computed value to the expected value.

49. The method of claim 45 wherein analyzing configuration data comprises:

computing a value based on the configuration data and the expected value; and

performing a logical operation on the computed value.

50. The method of claim 45 further comprising outputting a result of the analysis that indicates whether an error was detected.

51. The method of claim 45 wherein outputting the result comprises one of:

sending a first signal indicating that no error was detected; and

sending a second signal indicating that an error was detected.

52. Circuitry for accessing configuration data stored on a logic device and sending the configuration data to an output, comprising:

a memory in which the configuration data is stored, wherein the memory comprises frames of memory cells;

an address register capable of storing a number of bits at least equal to a number of the frames, wherein each bit stored in the address register is associated with a different frame of the frames of memory cells;

a data register coupled to the memory; and

control logic coupled to the memory, the address register, and the data register to access a particular frame of memory cells, wherein the control logic asserts a bit in the address register associated with the particular frame of memory cells, causes data from the particular frame of memory cells to be loaded into the data register, and causes a subset of data from the particular frame of memory cells to be loaded from the data register to the output.

53. The circuitry of claim 52 wherein the memory is random access memory.

54. The circuitry of claim 52 wherein the memory is arranged in an array comprising rows and columns of memory cells.

55. The circuitry of claim 54 wherein each frame of memory cells comprises a column of memory cells.

56. The circuitry of claim 54 wherein each memory cell in a row is coupled to a data line associated with that row that is input to the data register.

57. The circuitry of claim 56 wherein each data line is precharged to a predetermined voltage when data is to be read from the memory.

58. The circuitry of claim 57 wherein the data from the particular frame of memory cells is read onto the data lines and loaded into the data register.

59. The circuitry of claim 52 wherein the control logic sets an address line coupled to the particular frame of memory cells to enable data from the particular frame of memory cells to be loaded into the data register.

60. The circuitry of claim 52 wherein the control logic:

deasserts the bit in the address register associated with the particular frame of memory cells; and

asserts a next bit in the address register associated with a next frame of memory cells while the subset of the data from the particular frame of memory cells is being loaded from the data register to the output.

61. The circuitry of claim 60 wherein the control logic further:

enables remaining subsets of the data from the particular frame of memory cells to be loaded from the data register to the output over subsequent clock cycles.

62. The circuitry of claim 61 wherein the control logic further:

sets a next address line coupled to the next frame of memory cells to enable data from the next frame of memory cells to be loaded into the data register when a last subset of the data from the particular frame of memory cells is being loaded from the data register to the output.

63. The circuitry of claim 52 wherein the control logic is a finite state machine.

64. The circuitry of claim 52 wherein the output is coupled to an error detection circuit.

65. Control logic that controls the communication of configuration data stored in a memory to an output circuitry, wherein the memory comprises frames of memory cells, the control logic being coupled to:

the memory;

an address register in which each bit location is associated with a distinct frame of the frames of memory cells; and

a data register that is further coupled to the memory, wherein the control logic;

a. asserts a bit in the address register to indicate a selection of a particular frame of memory cells,

b. loads the particular frame of memory cells to the data register,

c. loads the particular frame of memory cells in the data register to the output circuitry, wherein the particular frame of memory cells is loaded to the output circuitry one portion per clock cycle at a time, and

d. repeats a-c for each frame of the frames of memory cells.

66. The control logic of claim 65 wherein the control logic also precharges each data line associated with a row of memory cells in the memory that is input to the data register when data is to be read from the memory.

67. The control logic of claim 66 wherein the particular frame of memory cells is read onto the data lines and loaded into the data register.

68. The control logic of claim 65 wherein the control logic also sets an address line coupled to the particular frame of memory cells in enable the particular frame of memory cells to be loaded into the data register.

69. The control logic of claim 65 wherein the control logic also:

deasserts the bit in the address register associated with the particular frame of memory cells; and

asserts a next bit in the address register associated with a next frame of memory cells while the portion of the particular frame of memory cells is being loaded to the output circuitry.

70. The control logic of claim 69 wherein the control logic further:

sets a next address line coupled to the next frame of memory cells to enable the next frame of memory cells to be loaded into the data register when a last portion of the particular frame of memory cells is being loaded to the output circuitry.

71. The control logic of claim 65 wherein the control logic is a finite state machine.

72. The control logic of claim 65 wherein the output circuitry is error detection circuitry.

73. A method for accessing configuration data stored on a logic device and sending the configuration data to an output using control logic, comprising:

asserting a bit in an address register associated with a particular frame of memory cells in a memory in which the configuration data is stored;

loading data from the particular frame of memory cells into a data register; and

loading a subset of the data from the particular frame of memory cells from the data register to the output.

74. The method of claim 73 further comprising associating each bit in the address register with a different frame of memory cells in the memory.

75. The method of claim 74 further comprising deasserting bits other than the bit in the address register associated with the particular frame of memory cells in the memory.

76. The method of claim 73 wherein loading data from the particular frame of memory cells into the data register comprises precharging data lines that extend across each row of memory cells in the memory and that is input to the data register.

77. The method of claim 76 further comprising reading the data from the particular frame of memory cells onto the data lines.

78. The method of claim 73 further comprising setting an address line coupled to the particular frame of memory cells to enable the data from the particular frame of memory cells to be loaded into the data register.

79. The method of claim 73 wherein loading the subset of the data from the particular frame of memory cells further comprises:

deasserting the bit in the address register associated with the particular frame of memory cells;

asserting a next bit in the address register associated with a next frame of memory cells.

80. The method of claim 79 further comprising:

loading remaining subsets of the data from the particular frame of memory cells from the data register to the output over subsequent clock cycles.

81. The method of claim 80 wherein loading a last subset of the data from the particular frame of memory cells further comprises:

setting a next address line coupled to the next frame of memory cells to enable data from the next frame of memory cells to be loaded into the data register.