Semiconductor device, semiconductor element and method for producing same

• US 20030098509A1
• Filed: 01/13/2003
• Published: 05/29/2003
• Est. Priority Date: 09/27/1999
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimizu, Kazuhiro, Shirota, Riichiro, Takeuchi, Yuji, Yaegashi, Toshitake, Arai, Norihisa, Kamiya, Eiji
• Application Number:
  US10/340,750
• Publication Number:
  US 20030098509A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of first diffusion layers having a low impurity density, said first diffusion layers being formed on the surface of said semiconductor substrate;

a plurality of second diffusion layers having a high impurity density, said second diffusion layers being formed on the surface of said semiconductor substrate;

a plurality of first contacts, each of which contacts said first diffusion layers and each of which is formed of a semiconductor; and

a plurality of second contacts, each of which contacts said second diffusion layers and each of which is formed of a metal.

2. A semiconductor device as set forth in claim 1, which further comprises a memory cell array and a peripheral circuit and wherein said plurality of first diffusion layers are formed in said memory cell array and a part of said peripheral circuit, and said plurality of second diffusion layers are formed in other part of said peripheral circuit.

3. A semiconductor device as set forth in claim 1, wherein each of said plurality of first diffusion layers is a diffusion layer, to which a high voltage is applied, and which is connected to a corresponding one of said first contacts of said semiconductor, and

said each of said plurality of second diffusion layers is a diffusion layer, to which a high voltage is not applied, and which is connected to a corresponding one of said second contacts of said metal.

4. A semiconductor device as set forth in claim 1, which further comprises:

a high voltage circuit having a plurality of MOS transistors having a thick gate insulating film; and

a low voltage circuit having a plurality of MOS transistors having a thin gate insulating film,

wherein each of said plurality of first contacts is formed in said high voltage circuit portion, and

each of said plurality of second contacts is formed in said low voltage circuit portion.

5. A semiconductor device as set forth in claim 1, wherein at least the bottom portion of each of said first contacts is formed of semiconductor material, said bottom portion being connected to a corresponding one of said first diffusion layers, and the remaining portion of each of said first contacts is formed of a metal.

6. A semiconductor device as set forth in claim 1, wherein said semiconductor material is a polycrystalline silicon or an amorphous silicon, and said metal is tungsten, aluminum or metal including at least one of tungsten, aluminum and titanium.

7. A method for producing a semiconductor device having a semiconductor filled contact or a metal filled contact for a plurality of diffusion layers, said method comprising the steps of:

forming a plurality of contact holes;

filling a semiconductor in each of said first contact holes;

carrying out a thermal treatment;

forming a plurality of second contact holes; and

filling a metal in each of said second contact holes.

8. A method as set forth in claim 7, which further comprises a step of etching back a part of the filled semiconductor to form a groove to fill the metal in the groove.

9. A method as set forth in claim 7, wherein said thermal treatment is carried out after said semiconductor is filled in each of said first contact holes.

10. A method as set forth in claim 7, which further comprises a step of injecting ions, which have the same conductive type as those of said diffusion layers, in said first contact holes to increase the density of said diffusion layers.

11. A semiconductor device comprising:

a memory cell part having a plurality of non-volatile memory cells, each of which has a floating gate electrode, a control gate and an insulating film arranged therebetween;

a peripheral circuit having a plurality of peripheral transistors each having a gate electrode made of the material of said floating gate electrode;

a plurality of cell gate contacts, each of which contacts a corresponding one of said control gate electrodes for activating a corresponding one of said memory cells; and

a plurality of peripheral gate contacts, each of which contacts a corresponding one of said floating gate electrodes for activating a corresponding one of said peripheral circuits, each of said peripheral gate contacts being electrically connected to both of said corresponding one of said floating gate electrodes and said corresponding one of said control gate electrodes.

12. A semiconductor device as set forth in claim 11, wherein the side face of each of said cell gate contacts is connected to said corresponding one of said control gate electrodes, and the bottom face thereof is connected to said corresponding one of said floating gate electrodes.

13. A semiconductor device as set forth in claim 11, wherein the side face of each of said peripheral gate contacts is connected to said corresponding one of said control gate electrodes and said corresponding one of said floating gate electrodes.

14. A semiconductor device as set forth in claim 11, wherein the side face of each of said cell gate contacts is connected to said corresponding one of said control gate electrodes.

15. A method for producing a semiconductor device which comprises a memory cell part having a plurality of non-volatile memory cells, each of which has a floating gate electrode, a control gate and an insulating film arranged therebetween;

a peripheral circuit having a plurality of peripheral transistors each having a gate electrode made of the material of said floating gate electrode;

a plurality of cell gate contacts, each of which contacts a corresponding one of said control gate electrodes for activating a corresponding one of said memory cells; and

a plurality of peripheral gate contacts, each of which contacts a corresponding one of said floating gate electrodes for activating a corresponding one of said peripheral circuits, each of said peripheral gate contacts being electrically connected to both of said corresponding one of said floating gate electrodes and said corresponding one of said control gate electrodes, said method comprising the steps of;

simultaneously etching said floating gate electrodes and said insulating films to form contact holes; and

filling a contact material in said contact holes to form said peripheral gate contacts.

16. A method for producing semiconductor device as set forth in claim 15, wherein both of said peripheral gate contacts and said cell gate contacts are formed at the same step.

17. A semiconductor device comprising a memory cell array including memory transistors having a double-layer gate structure, and select gate transistors serving as gates for transmitting and receiving data to and from said memory transistors, wherein contacts with the gate electrodes of said select gate transistors are formed of a polysilicon.

18. A semiconductor device as set forth in claim 17, wherein said polysilicon of said contacts with the gate electrodes of said select gate transistors is the same as a polysilicon, of which a source line contact or bit line contact of each of said memory cells is formed.

19. A semiconductor device as set forth in claim 17, wherein said contact formed of said polysilicon has a projecting portion which does not contact with a contact region of a corresponding one of said gate electrodes.

20. A semiconductor high resistive element formed in a semiconductor substrate, in said substrate double-layer electrode type transistors are formed by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode,

wherein a pair of contact holes are formed in at least a material layer of said second gate electrode and a material layer of said second gate insulating film of said four layers at regular intervals, a wiring material is filled in each of said pair of contact holes so as to be electrically connected to a material layer of said first gate electrode, and an insulating material is arranged on an inner surface of each of said pair of contact holes to electrically isolate said wiring material from said material layer of said second gate electrode, so that said material layer of said first gate electrode is used as a resistive material.

21. A semiconductor high resistive element formed in a semiconductor substrate, in said substrate double-layer electrode type transistors are formed by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode,

wherein a pair of contact holes are formed in at least a material layer of said second gate electrode and a material layer of said second gate insulating film of said four layers at regular intervals, a wiring material is filled in each of said pair of contact holes so as to be electrically connected to a material layer of said first gate electrode, and said material layer of said second gate electrode is electrically cut at least one place between said pair of contact holes, so that said material layer of said first gate electrode is used as a resistive material.

22. A method for producing a semiconductor element in a semiconductor substrate, in said substrate double-layer electrode type transistors are by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode on said semiconductor substrate, said method comprising the steps of:

forming an insulating film in a specific region on said semiconductor substrate;

sequentially forming three layers of a material layer of said first gate electrode, a material layer of said second gate insulating film, and a material layer of said second gate electrode, on said insulating film;

etching said material layer of said second gate electrode and said material layer of said gate insulating layer to form at least a pair of contact holes for exposing said material layer of said first gate electrode functioning as a resistive element material;

selectively forming another insulating film on side walls of said contact holes; and

filling a wiring material in said contact holes so that said wiring material is electrically insulated from said material layer of said second gate electrode by said another insulating film although said wiring material is electrically conducted to said material layer of said first gate electrode.

23. A method for producing a semiconductor element as set forth in claim 22, wherein said step of selectively forming said another insulating film on said side walls of said contact holes comprises the steps of:

depositing said another insulating film in said contact holes and on said protective insulating film; and

etching back said another insulating film to leave said another insulating film on said side walls of said contact holes.

24. A method for producing a semiconductor high resistive element as set forth in claim 22, wherein said another insulating film has a thickness which is half or less of a diameter of said contact holes.

25. A method for producing a semiconductor element in a semiconductor substrate, in said substrate double-layer electrode type transistors are by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode on said semiconductor substrate, said method comprising the steps of:

forming an insulating film in a specific region on said semiconductor substrate;

sequentially forming three layers of a material layer of said first gate electrode, a material layer of said second gate insulating film, and a material layer of said second gate electrode, on said insulating film;

etching, removing and cutting said material layer of said second gate electrode between a pair of contact hole intended regions to form a cut portion;

etching said material layer of said second gate electrode and said material layer of said gate insulating layer to form at least a pair of contact holes for exposing said material layer of said first gate electrode functioning as a resistive element material; and

filling a wiring material in said contact holes so that said wiring material is electrically conducted to said material layer of said first gate electrode.

26. A method for producing a semiconductor high resistive element as set forth in claim 25, which further comprises a step of introducing an impurity into said material layer of said first gate electrode through said cut portion to self-aligningly vary a resistance value of said material layer of said first gate electrode.

27. A method for producing a semiconductor high resistive element as set forth in claim 25, wherein said impurity introducing step is the same step as said step of forming said diffusion layer in a process for producing said double-layer electrode transistor.