Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges

• US 20030098716A1
• Filed: 01/03/2003
• Published: 05/29/2003
• Est. Priority Date: 08/03/2001
• Status: Active Grant

• Current Assignee: Dean D. Gans, John D. Porter, Larren G. Weber
• Original Assignee: Dean D. Gans, John D. Porter, Larren G. Weber
• Inventors: Porter, John D., Weber, Larren G., Gans, Dean D.
• Granted Patent: US 6,949,948 B2
• Time in Patent Office: Days
• US Class Current: 326/105
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

Claims

1. A memory device comprising:

decode circuitry for addressing memory cells in said memory device; and

at least one skewed logic device.

2. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed inverter rising logic device, said skewed inverter rising logic device comprising:

a fast inverter rising having a large p/n channel width ratio for receiving an input signal and rapidly propagating a rising edge onto an output signal in response to receiving a falling edge on said input signal;

a pull-down reset network connected in parallel with said fast inverter rising for resetting said output signal after said rising edge has been propagated onto said output signal; and

a feedback delay circuit connected in parallel with said pull-down reset network for delaying and returning said output signal back to said pull-down reset network.

3. The memory device of claim 2, wherein said large p/n channel width ratio ranges from about 5 to about 200.

4. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed inverter falling logic device, said skewed inverter falling logic device comprising:

a fast inverter falling having a large n/p channel width ratio for receiving an input signal and rapidly propagating a falling edge onto an output signal in response to receiving a rising edge on said input signal;

a pull-up reset network connected in parallel to said fast inverter falling for resetting said output signal after said falling edge has been propagated onto said output signal; and

a feedback delay circuit connected in parallel with said pull-up reset network for delaying and returning said output signal to said pull-up reset network.

5. The memory device of claim 4, wherein said large n/p channel width ratio ranges from about 5 to about 200.

6. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed buffer rising logic device, said skewed buffer rising logic device comprising:

a fast inverter falling having a large n/p channel width ratio for receiving a rising edge of an input signal and rapidly propagating a falling edge of an intermediate signal in response thereto;

a fast inverter rising having a large p/n channel width ratio and in series with said fast inverter falling for receiving said rapidly propagated falling edge of said intermediate signal and rapidly propagated a rising edge on an output signal;

a reset network coupled to said fast inverter falling and said fast inverter rising for resetting output signals of said fast inverter falling and said fast inverter rising after said rising edge of said output signal has been rapidly propagated; and

a feedback delay circuit operably coupled between an output of said fast inverter rising and an input of said reset network for propagating said output signal to said reset network.

7. The memory device of claim 6, wherein said large n/p channel width ratio ranges from about 5 to about 200.

8. The memory device of claim 6, wherein said large p/n channel width ratio ranges from about 5 to about 200.

9. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed buffer falling logic device, said skewed buffer falling logic device comprising:

a fast inverter rising having a large p/n channel width ratio for receiving a falling edge of an input signal and rapidly propagating a rising edge of an intermediate signal in response thereto;

a fast inverter falling having a large n/p channel width ratio and in series with said fast inverter rising for receiving said rapidly propagated rising edge of said intermediate signal and rapidly propagated a falling edge on an output signal;

a reset network coupled to said fast inverter rising and said fast inverter falling for resetting output signals of said fast inverter rising and said fast inverter falling after said falling edge of said output signal has been rapidly propagated; and

a feedback delay circuit operably coupled between an output of said fast inverter falling and an input of said reset network for propagating said output signal to said reset network.

10. The memory device of claim 9, wherein said large p/n channel width ratio ranges from about 5 to about 200.

11. The memory device of claim 9, wherein said large n/p channel width ratio ranges from about 5 to about 200.

12. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed NOR falling logic device, said skewed NOR falling logic device comprising:

a fast NOR gate falling having a large n/p channel width ratio for receiving a first input signal and a second input signal and rapidly propagating a falling edge of an output signal in response to a rising edge on either of said first input signal or said second input signal;

a pull-up reset network connected in parallel with said fast NOR gate falling for resetting said output signal; and

a feedback delay circuit connected in parallel with said pull-up reset network for propagating said output signal to an input of said pull-up reset network.

13. The memory device of claim 12, wherein said large n/p channel width ratio ranges from about 5 to about 200.

14. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed NOR rising logic device, said skewed NOR rising logic device comprising:

a fast NOR gate rising having a large p/n channel width ratio for receiving a first input signal and a second input signal and rapidly propagating a rising edge of an output signal in response to a falling edge on both of said first input signal and said second input signal;

a pull-down reset network connected in parallel with said fast NOR gate rising for resetting said output signal after said rising edge of said output signal has been propagated; and

a feedback delay circuit connected in parallel with said pull-down reset network for delaying and returning said output signal back to an input of said pull-down reset network.

15. The memory device of claim 14, wherein said large p/n channel width ratio ranges from about 5 to about 200.

16. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed NAND falling logic device, said skewed NAND falling logic device comprising:

a fast NAND gate falling having a large n/p channel width ratio for receiving both a first input signal and a second input signal and rapidly propagating a falling edge of an output signal in response to rising edges on both said first input signal and said second input signal;

a pull-up reset network connected in parallel with said fast NAND gate falling for resetting said output signal after said falling edge of said output signal has been propagated; and

a feedback delay circuit connected in parallel with said pull-up reset network for delaying and returning said output signal to an input of said pull-up reset network.

17. The memory device of claim 16, wherein said large n/p channel width ratio ranges from about 5 to about 200.

18. The memory device of claim 1, wherein said at least one skewed logic device comprises a skewed NAND rising logic device, said skewed NAND rising logic device comprising:

a fast NAND gate rising having a large p/n channel width ratio for receiving both a first input signal and a second input signal and rapidly propagating a rising edge of an output signal in response to falling edges on either said first input signal or said second input signal;

a pull-down reset network connected in parallel with said fast NAND gate rising for resetting said output signal after said rising edge of said output signal has been propagated; and

a feedback delay circuit connected in parallel with said pull-down reset network for delaying and returning said output signal to an input of said pull-down reset network.

19. The memory device of claim 18, wherein said large p/n channel width ratio ranges from about 5 to about 200.

20. The memory device of claim 1, wherein said memory device is selected from the group consisting of dynamic random access memory (DRAM), double data rate SDRAM (DDR SDRAM), RAMBUS®

DRAM (RDRAM®

), extended data-out DRAM (EDO DRAM), fast-page-mode DRAM (FPM DRAM), static random access memory (SRAM), SyncBurst™

SRAM, Zero Bus Turnaround™

SRAM (ZBT™

SRAM), Quad Data Rate™

SRAM (QDR™

SRAM), DDR synchronous SRAM (DDR SRAM) and nonvolatile electrically block-erasable programmable read only memory (Flash).