Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and methods including same

• US 20030098718A1
• Filed: 01/03/2003
• Published: 05/29/2003
• Est. Priority Date: 08/03/2001
• Status: Active Grant

• Current Assignee: Dean D. Gans, John D. Porter, Larren G. Weber
• Original Assignee: Dean D. Gans, John D. Porter, Larren G. Weber
• Inventors: Porter, John D., Weber, Larren G., Gans, Dean D.
• Granted Patent: US 6,972,589 B2
• Time in Patent Office: Days
• US Class Current: 326/112
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

Claims

1. A method for rapidly propagating a fast edge of an output signal through a skewed logic device, the method comprising:

providing a skewed logic device, comprising;

a fast gate configured for receiving at least one input signal and outputting said output signal;

a reset network connected in parallel to said fast gate for resetting said output signal; and

a feedback delay circuit connected in parallel with said reset network for delaying and returning said output signal to said reset network;

propagating a fast edge through said skewed logic device onto said output signal of said skewed logic device; and

resetting said output signal in response to a slow edge of said at least one input signal.

2. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed inverter rising logic device.

3. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed inverter falling logic device.

4. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed buffer rising logic device.

5. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed buffer falling logic device.

6. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed NOR rising logic device.

7. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed NOR falling logic device.

8. The method of claim 1, wherein providing said skewed logic device comprises providing a skewed NAND rising logic device.

9. The method of claim 2, wherein providing said skewed logic device comprises providing a skewed NAND falling logic device.