Input level adjust system and method

• US 20030098805A1
• Filed: 11/29/2000
• Published: 05/29/2003
• Est. Priority Date: 11/29/1999
• Status: Active Grant

• Current Assignee: Karl M. Bizjak
• Original Assignee: Karl M. Bizjak
• Inventors: Bizjak, Karl M.
• Granted Patent: US 7,190,292 B2
• Time in Patent Office: Days
• US Class Current: 341/139
• CPC Class Codes: H03G 3/32 the control being dependent upon ambient noise level or sound level
• CPC Class Codes: H03G 7/002 in untuned or low-frequency amplifiers, e.g. audio amplifiers H03G7/007, H03G7/001, H03G7/008, H03G7/02, H03G7/06 take precedence
• CPC Class Codes: H04R 2227/005 Audio distribution systems for home, i.e. multi-room use
• CPC Class Codes: H04R 25/356 Amplitude, e.g. amplitude shift or compression
• CPC Class Codes: H04R 27/00 Public address systems circuits for preventing acoustic reaction H04R3/02; circuits for distributing signals to loudspeakers H04R3/12; monitoring or testing arrangements for public address systems H04R29/007; amplifiers H03F

Abstract

A method of matching input amplitudes in a system wherein one or more of a plurality of inputs may be selected, with each input capable of having different characteristics, involving selecting an input signal and mapping the input signal to a predetermined signal amplitude through the use of level matching logic. The level matching logic may include a gain cell for increasing or decreasing the amplitude of the input signal.

Claims

1. An input level matching system comprising

an input for providing at least one signal,

level matching logic for mapping the at least one signal to a predetermined signal amplitude to generate a modified signal,

an output for providing the modified signal.

2. The input level matching system of claim 1 further including

signal processing logic for performing at least one of signal selection, filtering, or analog-to-digital conversion of the at least one input signal.

3. The input level matching system of claim 1 wherein the level matching logic includes a gain cell.

4. The input level matching system of claim 1 wherein the output of the gain cell is a 0 db signal.

5. The input level matching system of claim 3 wherein the gain cell operates to provide digital amplification.

6. The input level matching system of claim 3 wherein the gain cell operates to provide analog amplification.

7. The input level matching system of claim 3 further including

a clip signal,

clip detection logic responsive to the clip signal for comparing the clip signal to a threshold signal for detecting signal clipping at the output of the gain cell.

8. The input level matching system of claim 7 wherein the clip signal is a function of the input to the gain cell.

9. The input level matching system of claim 7 wherein the clip signal is a function of the output of the gain cell.

10. The input level matching system of claim 8 wherein the output of the gain cell is a 0 dB signal, and the gain of the gain cell may be adjusted to provide a current gain.

11. The input level matching system of claim 10 wherein the threshold signal is a function of a maximum 0 dB signal divided by the current gain of the gain cell.

12. The input level matching system of claim 9 wherein the output of the gain cell is a 0 dB signal, and the gain of the gain cell may be adjusted to provide a current gain.

13. The input level matching system of claim 12 wherein the clip signal is compared to a maximum 0 dB signal.

14. The input level matching system of claim 11 further including direct calculation logic for detecting when the clip detector detects a clipping condition and directly calculating a maximum permissible gain value.

15. The input level matching system of claim 11 further including gain reducing logic for reducing the current gain of the gain cell when the clip detector detects a clipping condition.

16. The input level matching system of claim 15 wherein the gain reducing logic is adjusted iteratively to reduce the gain to an acceptable level.

17. The input level matching system of claim 13 further including direct calculation logic for detecting when the clip detector detects a clipping condition and directly calculating a maximum permissible gain value.

18. The input level matching system of claim 13 further including gain reducing logic for reducing the current gain of the gain cell when the clip detector detects a clipping condition.

19. The input level matching system of claim 18 wherein the gain reducing logic is adjusted iteratively to reduce the gain to an acceptable level.

20. The input level matching system of claim 7 further including a clip detector counter.

21. The input level matching system of claim 20 further including signaling logic for indicating the occurrence of a clip condition.

22. The input level matching system of claim 1 further including bandsplit and equalization logic.

23. The input level matching system of claim 22 wherein equalization comprises scaling.

24. The input level matching system of claim 3 further including gain cell gain storage and wherein the gain cell provides a gain value such that at least one gain value can be stored in and retrieved from the gain storage.

25. The input level matching system of claim 24 wherein the at least one input signal comprises multiple input signals.

26. The input level matching system of claim 24 wherein a gain value can be stored for each of the multiple input signals.

27. The input level matching system of claim 26 wherein a plurality of gain values can be stored and retrieved for each of the multiple input signals.

28. The input level matching system of claim 25 wherein the multiple input signals are arranged in groups.

29. The input level matching system of claim 25 wherein the gain value for all input signals within a group is the same.

30. The input level matching system of claim 29 wherein the gain value for a group is determined by the maximum input signal within that group.