Signal distribution to a plurality of circuit units

• US 20030099093A1
• Filed: 11/15/2002
• Published: 05/29/2003
• Est. Priority Date: 11/26/2001
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Kuzmenka, Maksim
• Granted Patent: US 7,236,378 B2
• Time in Patent Office: Days
• US Class Current: 361/715
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/086 for inductive purposes, e.g. printed inductor with ferrite core
• CPC Class Codes: H05K 2203/0545 Pattern for applying drops or paste; Applying a pattern made of drops or paste using thick film techniques to apply conductive material by using a substrate with a shape pattern H05K3/1258

Abstract

A device for distributing a signal, in particular a clock signal or a command/address signal from a signal source to a plurality of circuit units, includes a transformer. The transformer has a primary winding receiving the signal from the signal source. Further, the transformer includes a plurality of secondary windings, which are arranged to interact with the primary winding to transfer the signal to the circuit units.

Claims

1. Device for distributing a signal from a signal source to a plurality of circuit units comprising a transformer, said transformer comprising:

a primary winding receiving the signal from the signal source; and

a plurality of secondary windings arranged to interact with the primary winding to transmit the signal to the circuit units.

2. Device in accordance with claim 1, wherein a capacitor is connected in parallel to the primary winding.

3. Device in accordance with claim 1, wherein the signal source is a clock-signal source comprising a phase-locked loop, and wherein a further secondary winding is provided, which interacts with the primary winding to generate a feedback signal to the phase-locked loop.

4. Device in accordance with claim 1, wherein the primary winding and the secondary winding are formed by conductive traces of a printed circuit.

5. Device in accordance with claim 4, wherein the printed circuit comprises a magnetic core for improving the magnetic coupling between the primary winding and the secondary windings.

6. Device in accordance with claim 4, wherein the printed circuit comprises several layers, wherein the primary windings and the secondary winding are arranged on the same layer or adjacent layers.

7. Device in accordance with claims 1, wherein each secondary winding is connected to one of the circuit units via connection lines, wherein the arrangement of secondary winding and connection line for each circuit unit comprises an essentially identical topology.

8. Device in accordance with claim 1, wherein the circuit units are memory chips.

9. Device in accordance with claim 1, wherein the signal source is a clock-signal source or a command/address signal source.

10. Device in accordance with claim 1, wherein the primary winding is arranged on a board and wherein the secondary windings are arranged on the circuit units.