Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs
First Claim
1. A test apparatus for an integrated circuit wafer, comprising:
- a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface;
a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection;
at least one intermediate connector located between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate; and
a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member;
wherein the probe chip substrate is supported by the compliant member relative to the motherboard.
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Abstract
Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.
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Citations
179 Claims
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1. A test apparatus for an integrated circuit wafer, comprising:
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a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface;
a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection;
at least one intermediate connector located between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate; and
a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member;
wherein the probe chip substrate is supported by the compliant member relative to the motherboard. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67)
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68. A test apparatus for an integrated circuit wafer, the test apparatus connectable to a prober, comprising:
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a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface;
a probe chip substrate having a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection, wherein the plurality of electrical contacts on the connector surface contact at least one of the plurality of electrical conductors on the bottom surface of the motherboard; and
a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member;
wherein the probe chip substrate is supported by the compliant member relative to the motherboard. - View Dependent Claims (69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108)
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109. A decal assembly process, comprising the steps of:
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providing a probe chip substrate having an outer periphery and an inner region, and having a probe surface and a connector surface, a plurality of probe springs on the probe surface within the inner region, a plurality of electrical contacts on the connector surface within the inner region, wherein each of the probe springs is electrically connected to at least one electrical contact;
providing a compliant substrate having a defined attachment region; and
attaching the defined connection region of the compliant substrate to the outer periphery of the probe chip substrate.
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110. A decal assembly process, comprising the steps of:
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providing a probe chip substrate having an outer periphery and an inner region, and having a probe surface and a connector surface, a plurality of probe springs on the probe surface within the inner region, and a plurality of electrical contacts on the connector surface within the inner region, wherein each of the probe springs is electrically connected to at least one electrical contact;
applying an adhesive to the outer periphery of the connector surface of the probe chip substrate;
providing a mounting ring having an opening defined there through, the opening larger than the outer periphery of the probe chip substrate;
attaching a compliant member across the mounting ring;
adhesively attaching compliant member to the applied adhesive on the outer periphery of the probe chip substrate.
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111. A package for connection to an integrated circuit device, comprising:
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a package substrate having a first surface and a second surface;
a plurality of electrical connections extending through the package substrate between the first surface and the second surface; and
a plurality of probe springs located on the first surface and extending from the electrical connections, the plurality of probe springs being at least temporarily connectable to at least one integrated circuit device. - View Dependent Claims (112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135)
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136. A method for developing a probe assembly for connection to at least one device on a wafer, comprising the steps of:
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providing a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the top surface to the bottom surface;
providing at least one standard intermediate connector having an upper interface and a lower interface, the upper surface locatable proximate to the bottom surface of the motherboard substrate, the intermediate connector comprising at least one electrically conductive connection between the upper interface and the lower interface corresponding to each of the electrical conductors on the bottom surface of the motherboard substrate;
providing a probe chip substrate design comprising a connector surface, a probe surface opposite the connector surface, and a plurality of contacts on the connector surface arranged in a fixed layout, the connector surface locatable proximate to the lower surface of the intermediate connector;
receiving an interconnection specification for the at least one device on the wafer, the interconnection specification comprising electrical interconnection locations for the at least one device; and
producing a probe chip substrate, wherein the substrate is based upon the probe chip substrate design, wherein the probe chip substrate further comprises a plurality of probe springs on the probe surface corresponding to the interconnection locations on the wafer, and wherein each of the probe springs is electrically connected to at least one contact on the connector surface. - View Dependent Claims (137, 138, 139, 140, 141, 142, 143, 144)
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145. A probe assembly structure for electrical connection to interconnection locations on a wafer, comprising:
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a master slice comprising at least one substrate having standardized electrical connections; and
at least one customized interface connectable to the master slice, the customized interface comprising a plurality of probe springs corresponding to the interconnection locations, and wherein each of the probe springs is electrically connected to at least one standardized electrical connection on the master slice. - View Dependent Claims (146, 147, 148, 149, 150)
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151. A method for developing a probe assembly for connection to at least one device on a wafer, comprising the steps of:
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providing a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the top surface to the bottom surface;
providing a probe chip substrate design comprising a connector surface and a probe surface opposite the connector surface, and a plurality of contacts on the connector substrate arranged in a fixed layout, the connector surface locatable proximate to the lower surface of the motherboard substrate;
receiving an interconnection specification for the at least one device on the wafer, the interconnection specification comprising electrical interconnection locations; and
producing a probe chip substrate, wherein the substrate is based upon the probe chip substrate design, wherein the probe chip substrate further comprises a plurality of probe springs on the probe surface corresponding to the interconnections on the wafer, and wherein each of the probe springs is electrically connected to at least one contact on the connector surface. - View Dependent Claims (152, 153, 154, 155, 156, 157, 158)
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159. An interposer, comprising:
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a compliant membrane comprising an inner region and an outer peripheral region on either side of said inner region, the inner region defining an array of apertures through the membrane;
at least one pair of electrically interconnected, compliant probe springs, each comprising a planar base region and a nonplanar region;
wherein said at least one pair of compliant probe springs are attached to the compliant membrane at the planar base region thereof; and
wherein the non-planar regions of the probe spring pair extend from each other in substantially opposite directions though corresponding apertures in the compliant membrane. - View Dependent Claims (160, 161, 162, 163, 164, 165, 166, 167, 168)
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169. An interposer, comprising:
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an interposer substrate having a first surface and a second surface;
at least one electrically conductive via extending through the interposer substrate from the first surface to the second surface;
at least one electrically conductive first compliant probe spring formed on the first surface of the interposer substrate comprising a first plurality of layers formed with different stress levels, which layers retain such stress until lifted, said probe spring comprising a planar region and a nonplanar region, the non-planar region formed from an inherent stress gradient within said layers;
at least one electrically conductive second compliant probe spring located on a second surface of the interposer substrate, the second compliant probe spring comprising a second plurality of layers formed with different stress levels, which layers retain such stress until lifted, said probe spring comprising a planar region and a nonplanar region, the non-planar region formed from an inherent stress gradient within said layers; and
at least one redundant electrically conductive element;
wherein the first compliant probe spring is in electrical contact with the second compliant probe spring through at least one of the electrically conductive vias. - View Dependent Claims (170, 171, 172, 173, 174, 175, 176, 177, 178)
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179. A process of forming an interposer, comprising the steps of:
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providing a substrate;
forming a first release layer on the substrate;
forming a first plurality of electrically conducting stress layers on the first release layer having an inherent stress gradient comprising a downward peeling stress;
selectively forming a second release layer over the first plurality of stress layers;
forming a second plurality of electrically conducting stress layers on the second release layer having an inherent stress gradient comprising an upward peeling stress;
patterning at least one finger region in the first plurality of stress layers and the overlying second plurality of stress layers;
selectively forming a compliant membrane having an inner region and a peripheral region, the inner region comprising an array of through holes surrounded by non-perforated solid portion, wherein the non-perforated solid portion covering a portion of the finger region at one end, and the through hole portion is positioned over the remaining portion of the finger region;
a rigid support ring is attached to the peripheral region of the compliant membrane, holding the compliant membrane in tension;
etching the release layers;
wherein said finger region defines an opening through which substantially opposed, electrically interconnected compliant probe springs project.
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Specification