Cascaded delay locked loop circuit
First Claim
Patent Images
1. A delay locked loop circuit, comprising:
- a primary delay line having a plurality of primary output taps; and
a secondary delay circuit having a plurality of secondary output taps, the secondary delay circuit further having an input that receives a signal from a selected one of the primary output taps.
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Accused Products
Abstract
A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
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Citations
107 Claims
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1. A delay locked loop circuit, comprising:
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a primary delay line having a plurality of primary output taps; and
a secondary delay circuit having a plurality of secondary output taps, the secondary delay circuit further having an input that receives a signal from a selected one of the primary output taps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A delay locked loop circuit, comprising:
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a primary delay line having an input that receives a clock signal, and having an output and having a plurality of N primary output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×
D;
a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay N×
D to a delay that locks the delay locked loop;
a secondary delay circuit having an input receiving a signal from a selected one of the N output taps, and a plurality of M secondary output taps at each of a plurality of delay elements each having a delay Ds, the secondary delay circuit having a total delay of M×
Ds; and
an output control circuit that selects one or more output taps from either the primary delay line or the secondary delay circuit as an output. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A delay locked loop circuit, comprising:
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a primary delay line having an input that receives a clock signal, and having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×
D;
a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay N×
D to a delay that locks the delay locked loop;
a plurality of secondary delay circuits, each having an input receiving a signal from one of the N output taps, and each delay element having a plurality of M output taps at each of a plurality of delay elements each having a delay Ds, each of the secondary delay circuits having a total delay of M×
Ds; and
an output control circuit that selects one or more taps from either the primary delay line or the secondary delay circuit as an output. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A delay locked loop circuit, comprising:
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a primary delay line having a plurality of N primary output taps;
an N;
1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal; and
a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67)
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68. A delay locked loop circuit, comprising:
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a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×
D;
a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that is applied to the control input that sets the total delay to a delay that locks the delay locked loop;
an N;
1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal;
a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of M passive delay elements each having a delay Dp, the secondary delay circuit having a total delay of approximately M×
Dp; and
an output control circuit that selects one or more taps from the primary delay line and the secondary delay circuit as an output. - View Dependent Claims (69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
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88. A delay locked loop circuit, comprising:
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a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of N delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×
D;
a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay to a delay that locks the delay locked loop circuit;
an N;
1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal;
a secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of delay elements each having a delay Ds, the secondary delay circuit having a total delay of M×
Ds, where M×
Ds is different than N×
D; and
an output control circuit that selects one or more output taps from either the primary delay line or the secondary delay circuit as an output. - View Dependent Claims (89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101)
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102. A method of selecting output taps in a delay locked loop frequency synthesizer having a primary delay line forming part of a primary delay locked loop and one or more secondary delay lines forming one or more secondary delay locked loops, comprising:
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computing a ratio K.C of the clock signal'"'"'s frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and
identifying a sequence of taps constituting a repeating tap cycle in the one or more secondary delay lines at approximately equally spaced delay increments, wherein a jth tap address Cj is defined by Cj=Cj−
1+C. - View Dependent Claims (103, 104)
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105. A method of tuning a frequency synthesizer, the frequency synthesizer having a primary delay locked loop (DLL) having a primary delay line with N delay elements each with approximately D seconds of delay, the synthesizer having a passive secondary delay line delay having a total delay of approximately D seconds, the method comprising:
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locking the DLL to a reference clock;
fixing a control signal to the primary delay line at a signal level to maintain a delay of N×
D, approximating the period of the reference clock;
substituting the passive secondary delay line for a selected one of the delay elements of the primary delay line; and
adjusting the delay of the passive secondary delay line to a locked condition of the DLL. - View Dependent Claims (106, 107)
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Specification
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Current AssigneeMotorola Solutions, Inc.
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Original AssigneeMotorola, Inc. (Motorola Solutions, Inc.)
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InventorsBockelman, David E., Stengel, Robert E., Martin, Frederick L., Juan, Jui-Kuo
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current375/376
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CPC Class CodesH03L 2207/08 Modifications of the phase-...H03L 7/07 using several loops, e.g. f...H03L 7/0816 the controlled phase shifte...H03L 7/0818 the controlled phase shifte...H03L 7/14 for assuring constant frequ...H03L 7/16 Indirect frequency synthesi...
