Method for forming capacitor of semiconductor device

• US 20030100162A1
• Filed: 11/01/2002
• Published: 05/29/2003
• Est. Priority Date: 11/28/2001
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Joo, Kwang-Chul
• Application Number:
  US10/285,587
• Publication Number:
  US 20030100162A1
• Time in Patent Office: Days
• US Class Current: 438/396
• CPC Class Codes: C23C 16/34 Nitrides C23C16/303 takes precedence
• CPC Class Codes: C23C 16/45527 characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

The present invention is related to a method for forming a capacitor of a semiconductor device capable of obtaining an excellent electronic property corresponding to a high degree of integration by forming a Ta₃N₅ thin film having a greater dielectric constant than Ta₂O₅ and TaON thin films through an atomic layer deposition (ALD). Particularly, the Ta₃N₅ thin film is a dielectric layer of the capacitor. The inventive method, including the steps of: forming a bottom electrode coupled to an active area of a semiconductor substrate; performing an atomic layer deposition (ALD) technique to form a Ta₃N₅ dielectric layer with use of a gas precursor of TaCl₅ on the bottom electrode; and forming a top electrode on the Ta₃N₅ dielectric layer.

Claims

1. A method for forming a capacitor of a semiconductor device, comprising the steps of:

forming a bottom electrode coupled to an active area of a semiconductor substrate;

performing an atomic layer deposition (ALD) technique to form a Ta₃N₅ dielectric layer with use of a gas precursor of TaCl₅ on the bottom electrode; and

forming a top electrode on the Ta₃N₅ dielectric layer.

2. The method as recited in claim 1, further comprising the step of forming a nitride layer on the bottom electrode by performing a nitridation process, after forming the bottom electrode.

3. The method as recited in claim 2, wherein the nitride layer is formed having a thickness ranging from about 5 Å

to about 30 Å

.

4. The method as recited in claim 2, wherein the nitridation process is performed through a plasma process, a rapid thermal process or a furnace process.

5. The method as recited in claim 4, wherein the plasma process is performed at a temperature ranging from about 300°

C. to about 600°

C. in an ambient of NH₃ or N₂/H₂ for about 30 seconds to about 5 minutes.

6. The method as recited in claim 4, wherein the rapid thermal process is performed at a temperature ranging from about 650°

C. to about 950°

C. in a NH₃ ambient.

7. The method as recited in claim 4, wherein the furnace process is performed at a temperature ranging from about 500°

C. to about 1000°

C. in a NH₃ ambient.

8. The method as recited in claim 1, wherein the Ta₃N₅ dielectric layer is formed with use of a reactant gas NH₃.

9. The method as recited in claim 8, wherein the TaCl₅ gas precursors and the reactant gas are controlled to maintain their flow quantities within a range between about 10 sccm to about 500 sccm.

10. The method as recited in claim 9, wherein the Ta₃N₅ dielectric layer is formed with a growth rate ranging from about 0.1 Å

to about 0.5 Å

per cycle.

11. The method as recited in claim 1, further comprising the step of oxidating the Ta₃N₅ dielectric layer, after forming the Ta₃N₅ dielectric layer.

12. The method as recited in claim 11, the oxidation process is performed with use of any one of a plasma process, a rapid thermal process or a furnace process.

13. The method as recited in claim 12, wherein the plasma process is performed at a temperature within a range from about 300°

C. to about 600°

C. in an ambient of N₂O or O₂.

14. The method as recited in claim 12, wherein the rapid thermal process is performed at a temperature within a range from about 600°

C. to about 950°

C. in an ambient of any of one selected gas from a group of N₂O, O₂ and N₂ for 30 seconds to 10 minutes.

15. The method as recited in claim 12, the furnace process is performed at a temperature within a range from about 600°

C. to about 950°

C. in an ambient of any of one selected gas from a group consisting of N₂O, O₂ and N₂ for about one minute to about 120 minutes.

16. The method as recited in claim 11, wherein the oxidation process is executed with a light wet oxidation operation in an ambient of O₂/H₂ by fixing a quantity of O₂/H₂ gas flow ratio to be less than about 3.

17. The method as recited in claim 1, wherein the top electrode is made of any of one selected from a group consisting of TaN, TiN, W, WN, WSi, Ru, RuO₂, Ir, IrO₂, and Pt.

18. The method as recited in claim 1, wherein the top electrode has a thickness ranging from about 100 Å

to about 600 Å

.

19. The method as recited in claim 1, further comprising the step of forming a buffer layer with a doped polysilicon layer on the top electrode, after forming the top electrode.

20. The method as recited in claim 1, wherein the Ta₃N₅ dielectric layer is formed on the bottom electrode of which a surface is processed with HF and a native oxide layer on the surface is removed.