Buried solder bumps for AC-coupled microelectronic interconnects

• US 20030100200A1
• Filed: 11/28/2001
• Published: 05/29/2003
• Est. Priority Date: 11/28/2001
• Status: Active Grant

• Current Assignee: North Carolina State University (University of North Carolina System)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Mick, Stephen E., Wilson, John M., Franzon, Paul D.
• Granted Patent: US 6,885,090 B2
• Time in Patent Office: Days
• US Class Current: 439/66
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 1/0239 : Signal transmission by AC coupling
• CPC Class Codes: H05K 1/0243 : Printed circuits associated with mounted high frequency components
• CPC Class Codes: H05K 1/0263 : High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 2201/09036 : Recesses or grooves in insulating substrate
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting; Recessed electrode of component
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Claims

1. A microelectronic package comprising:

a first microelectronic substrate including a first face and a first AC-coupled interconnect element on the first face;

a second microelectronic substrate including a second face and a second AC-coupled interconnect element on the second face; and

a buried solder bump that extends between the first and second faces and that is at least partially buried beneath at least one of the first and second faces to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation.

2. A microelectronic package according to claim 1 wherein the first AC-coupled interconnect element comprises a first capacitor plate and wherein the second AC-coupled interconnect element comprises a second capacitor plate.

3. A microelectronic package according to claim 1 wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor.

4. A microelectronic package according to claim 1 wherein the first AC-coupled interconnect element comprises a first combined inductive and capacitive element and wherein the second AC-coupled interconnect element comprises a second combined inductive and capacitive element.

5. A microelectronic package according to claim 1 further comprising a trench in the second face, including a trench floor beneath the second face, the buried solder bump extending between the trench floor and the first face.

6. A microelectronic package according to claim 1 further comprising:

a first trench in the first face, including a first trench floor beneath the first face; and

a second trench in the second face, including a second trench floor beneath the second face;

wherein the buried solder bump extends between the first trench floor and the second trench floor.

7. A microelectronic package according to claim 5 further comprising:

a first solder bump pad on the trench floor and a second solder bump pad on the first face, the buried solder bump extending between the first solder bump pad and the second solder bump pad.

8. A microelectronic package according to claim 6 further comprising:

a first solder bump pad on the first trench floor and a second solder bump pad on the second trench floor, the buried solder bump extending between the first solder bump pad and the second solder bump pad.

9. A microelectronic package according to claim 1 wherein the first microelectronic substrate is an integrated circuit and wherein the second microelectronic substrate is a second level package for the integrated circuit.

10. A microelectronic package according to claim 9 wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor having greater inductance than the first inductor.

11. A microelectronic package according to claim 1 further comprising a DC offset compensating receiver in at least one of the first and second substrates that is coupled to the corresponding at least one of the first and second AC-coupled interconnect elements.

12. A microelectronic package according to claim 3 further comprising a current mode driver in at least one of the first and second substrates that is coupled to the corresponding at least one of the first and second inductors.

13. A microelectronic package according to claim 4 further comprising a current mode driver in at least one of the first and second substrates that is coupled to the corresponding at least one of the first and second combined inductive and capacitive elements.

14. A microelectronic package according to claim 1 wherein the buried solder bump is further configured to transfer DC power between the first and second substrates.

15. A microelectronic package according to claim 1 wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled signal interconnect elements.

16. A microelectronic package according to claim 1 wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled power interconnect elements.

17. A microelectronic package according to claim 3 further comprising a first mutual inductance coupling element on the first inductor opposite the first substrate, and a second mutual inductance coupling element on the second inductor opposite the second substrate.

18. A microelectronic package according to claim 4 further comprising a first mutual inductance coupling element on the first combined inductive and capacitive element opposite the first substrate, and a second mutual inductance coupling element on the second combined inductive and capacitive element opposite the second substrate.

19. A microelectronic package comprising:

a microelectronic substrate including a face and an AC-coupled interconnect element on the face; and

a buried solder bump that is at least partially buried beneath the first face.

20. A microelectronic package according to claim 19 wherein the AC-coupled interconnect element comprises a capacitor plate.

21. A microelectronic package according to claim 19 wherein the AC-coupled interconnect element comprises an inductor.

22. A microelectronic package according to claim 19 wherein the AC-coupled interconnect element comprises a combined inductive and capacitive element.

23. A microelectronic package according to claim 19 further comprising a trench in the face, and including a trench floor beneath the face, the buried solder bump being on the trench floor.

24. A microelectronic package according to claim 23 further comprising:

a solder bump pad on the trench floor, the buried solder bump being on the first solder bump pad.

25. A microelectronic package according to claim 19 wherein the AC-coupled interconnect element comprises an AC-coupled signal interconnect element.

26. A microelectronic package according to claim 19 further comprising:

a DC power supply circuit that is electrically coupled to the buried solder bump.

27. A microelectronic package according to claim 19 further comprising a DC offset compensating receiver in the substrate that is coupled to the AC-coupled interconnect element.

28. A microelectronic package according to claim 21 further comprising a current mode driver in the substrate that is coupled to the inductor.

29. A microelectronic package according to claim 22 further comprising a current mode driver in the substrate that is coupled to the combined inductive and capacitive element.

30. A microelectronic package according to claim 21 further comprising a mutual inductance coupling element on the inductor opposite the substrate.

31. A microelectronic package according to claim 22 further comprising a mutual inductance coupling element on the combined inductive and capacitive element opposite the substrate.

32. A microelectronic package comprising:

a microelectronic substrate including a face and a trench in the face, including a trench floor beneath the face;

an AC-coupled interconnect element on the face; and

a solder bump pad on the trench floor.

33. A microelectronic package according to claim 32 further comprising:

a solder bump on the solder bump pad.

34. A microelectronic package according to claim 32 wherein the AC-coupled interconnect element comprises a capacitor plate.

35. A microelectronic package according to claim 32 wherein the AC-coupled interconnect element comprises an inductor.

36. A microelectronic package according to claim 32 wherein the AC-coupled interconnect element comprises a combined inductive and capacitive element.

37. A microelectronic package according to claim 32 wherein the AC-coupled interconnect element comprises an AC-coupled signal interconnect element.

38. A microelectronic package according to claim 32 further comprising:

a DC power supply circuit that is electrically coupled to the buried solder bump.

39. A microelectronic package according to claim 32 further comprising a DC offset compensating receiver in the substrate that is coupled to the AC-coupled interconnect element.

40. A microelectronic package according to claim 35 further comprising a current mode driver in the substrate that is coupled to the inductor.

41. A microelectronic package according to claim 36 further comprising a current mode driver in the substrate that is coupled to the combined inductive and capacitive element.

42. A microelectronic package according to claim 35 further comprising a mutual inductance coupling element on the inductor opposite the substrate.

43. A microelectronic package according to claim 36 further comprising a mutual inductance coupling element on the combined inductive and capacitive element opposite the substrate.

44. A microelectronic package comprising:

a first microelectronic substrate including a first face;

a first inductor on the first face;

a digital signal driver in the first microelectronic substrate that is configured to drive the first inductor with a digital signal;

a second microelectronic substrate including a second face;

a second inductor on the second face that is closely spaced apart from the first inductor; and

a digital signal receiver in the second microelectronic substrate that is configured to receive the digital signal from the digital signal driver via inductive coupling between the first and second inductors.

45. A microelectronic package according to claim 44 further comprising:

a buried solder bump that extends between the first and second faces and that is at least partially buried beneath at least one of the first and second faces to maintain the first and second inductors in closely spaced apart relation.

46. A microelectronic package according to claim 44 wherein the first and second inductors also include capacitance associated therewith.

47. A microelectronic package according to claim 44 wherein the first microelectronic substrate is an integrated circuit and wherein the second microelectronic substrate is a second level package for the integrated circuit.

48. A microelectronic package according to claim 47 wherein the second inductor has greater inductance than the first inductor.

49. A microelectronic package according to claim 44 wherein the digital signal receiver is a DC offset compensating digital signal receiver.

50. A microelectronic package according to claim 44 wherein the digital signal driver is a current mode digital signal driver.

51. A microelectronic package according to claim 44 further comprising a first mutual inductance coupling element on the first inductor opposite the first substrate, and a second mutual inductance coupling element on the second inductor opposite the second substrate.

52. A microelectronic package comprising:

a first microelectronic substrate including a first face and a first AC-coupled interconnect element on the first face;

a second microelectronic substrate including a second face and a second AC-coupled interconnect element on the second face;

a solder bump having a solder bump thickness and that extends between the first and second substrates; and

means for maintaining the first and second AC-coupled interconnect elements spaced apart from one another by a distance that is less than the solder bump thickness.

53. A microelectronic package according to claim 52 wherein the first AC-coupled interconnect element comprises a first capacitor plate and wherein the second AC-coupled interconnect element comprises a second capacitor plate.

54. A microelectronic package according to claim 52 wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor.

55. A microelectronic package according to claim 52 wherein the first AC-coupled interconnect element comprises a first combined inductive and capacitive element and wherein the second AC-coupled interconnect element comprises a second combined inductive and capacitive element.

56. A microelectronic package according to claim 52 wherein the first microelectronic substrate is an integrated circuit and wherein the second microelectronic substrate is a second level package for the integrated circuit.

57. A microelectronic package according to claim 54 wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor having greater inductance than the first inductor.

58. A microelectronic package according to claim 52 further comprising a DC offset compensating receiver in at least one of the first and second substrates and coupled to the corresponding at least one of the first and second AC-coupled interconnect elements.

59. A microelectronic package according to claim 54 further comprising a current mode driver in at least one of the first and second substrates and coupled to the corresponding at least one of the first and second inductors.

60. A microelectronic package according to claim 55 further comprising a current mode driver in at least one of the first and second substrates that is coupled to the corresponding at least one of the first and second combined inductive and capacitive elements.

61. A microelectronic package according to claim 52 wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled signal interconnect elements.

62. A microelectronic package according to claim 52 wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled power interconnect elements.

63. A microelectronic package according to claim 54 further comprising a first mutual inductance coupling element on the first inductor opposite the first substrate, and a second mutual inductance coupling element on the second inductor opposite the second substrate.

64. A microelectronic package according to claim 55 further comprising a first mutual inductance coupling element on the first combined inductive and capacitive element opposite the first substrate, and a second mutual inductance coupling element on the second combined inductive and capacitive element opposite the second substrate.

65. A microelectronic package comprising:

a first microelectronic substrate including a first face and a first AC-coupled interconnect element on the first face;

a second microelectronic substrate including a second face and a second AC-coupled interconnect element on the second face; and

an electrically conductive structure that extends between the first and second substrates and that is configured to maintain the first and second AC-coupled interconnect elements spaced apart from one another and is also configured to transfer DC power between the first and second substrates.

66. A microelectronic package according to claim 65 wherein the electrically conductive structure comprises a solder bump.

67. A microelectronic package according to claim 65 wherein the first AC-coupled interconnect element comprises a first capacitor plate and wherein the second AC-coupled interconnect element comprises a second capacitor plate.

68. A microelectronic package according to claim 65 wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor.

69. A microelectronic package according to claim 65 wherein the first AC-coupled interconnect element comprises a first combined inductive and capacitive element and wherein the second AC-coupled interconnect element comprises a second combined inductive and capacitive element.

70. A microelectronic package according to claim 65 wherein the first microelectronic substrate is an integrated circuit and wherein the second microelectronic substrate is a second level package for the integrated circuit.

71. A microelectronic package according to claim 68 wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor having greater inductance than the first inductor.

72. A microelectronic package according to claim 65 wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled signal interconnect elements.

73. A microelectronic package according to claim 68 further comprising a first mutual inductance coupling element on the first inductor opposite the first substrate, and a second mutual inductance coupling element on the second inductor opposite the second substrate.

74. A microelectronic package according to claim 69 further comprising a first mutual inductance coupling element on the first combined inductive and capacitive element opposite the first substrate, and a second mutual inductance coupling element on the second combined inductive and capacitive element opposite the second substrate.

75. An electrical connector comprising:

a first mating connector substrate including a first mating connector face;

a first array of inductors on the first mating face;

a second mating connector substrate including a second mating connector face; and

a second array of inductors on the second mating face;

the first and second mating connector substrates being configured to maintain the first and second mating connector faces in closely spaced apart relation to provide inductive coupling between corresponding inductors in the first and second arrays of inductors.

76. An electrical connector according to claim 75 further comprising at least one pin and at least one corresponding pin clip on at least one of the first and second mating connector substrates and configured to maintain the first and second mating connector faces in closely spaced apart relation.

77. An electrical connector according to claim 75 wherein the inductors in the first and second arrays of inductors also include capacitance associated therewith.