System and method for reduced deviation time domain FM/PM discriminator to achieve a reduced bandwidth frequency or phase modulation communications channels

• US 20030100278A1
• Filed: 10/04/2002
• Published: 05/29/2003
• Est. Priority Date: 10/06/2001
• Status: Active Grant

• Current Assignee: Alan Jack Herr, Patrick Owen Devaney
• Original Assignee: Alan Jack Herr, Patrick Owen Devaney
• Inventors: Herr, Alan Jack, Devaney, Patrick Owen
• Granted Patent: US 7,272,368 B2
• Time in Patent Office: Days
• US Class Current: 455/131
• CPC Class Codes: H03D 3/04 by counting or integrating cycles of oscillations arrangements for measuring frequencies G01R23/10

Abstract

The present disclosure provides a receiver for receiving a narrow frequency deviation frequency modulated or phase modulated base band signal including a mixer for mixing the received narrow frequency deviation signal to generate an intermediate frequency signal, a band pass filter for filtering the intermediate frequency signal, and a narrow band discriminator circuit that performs a time domain expansion of the modulation deviation of the intermediate frequency signal and discriminates the base band signal.

Claims

1. A receiver for receiving a narrow frequency deviation frequency modulated or phase modulated base band signal comprising:

a mixer for mixing the received narrow frequency deviation signal to generate an intermediate frequency signal;

a band pass filter for filtering the intermediate frequency signal;

a narrow band discriminator circuit that performs a time domain expansion of the modulation deviation of the intermediate frequency signal and discriminates the base band signal.

2. The device of claim 1 wherein the narrow band discriminator circuit comprises:

an analog to logic level converter for receiving the reduced deviation modulated signal;

a pulse generator that generates pulses with a fixed duration of one half the center frequency period of the intermediate frequency signal;

an exclusive-OR gate that receives an output of the logic level converter and the pulse generator;

an AND gate that receives an output of the exclusive-OR gate and a clock signal on each of its inputs;

a counter comprising an up/down input for indicating whether the counter counts up or down and is attached to the analog to logic level converter output, a clock input attached to the AND gate output, and a clear input attached to a control circuit, the counter further comprising N parallel outputs;

a latch comprising N parallel inputs and connected to the N parallel outputs of the counter and further comprising a clock input attached to an output of the control circuit and N parallel outputs; and

wherein the control circuit clocks the data from the counter to the latch on the positive transition of the intermediate frequency signal, and sequentially clears the counter.

3. The device of claim 2 further comprising a digital signal processor for receiving the N parallel outputs of the latch.

4. The device of claim 2 further comprising a digital to analog converter for receiving the N parallel outputs of the latch and a base band amplifier for amplifying an output of the digital to analog converter.

5. The device of claim 2 further comprising an accumulator and an accumulator latch interposed between the counter and the latch for receiving the N parallel outputs of the counter, the N parallel outputs of the accumulator latch to generate N parallel inputs to the second accumulator input port and the latch receives the N parallel outputs of the accumulator latch.

6. The device of claim 1 wherein the narrow band discriminator circuit comprises:

an analog to logic level converter for receiving the reduced deviation modulated signal;

a pulse generator that generates pulses with a fixed duration of one half the center frequency period of the intermediate frequency signal;

an exclusive-OR gate that receives an output of the logic level converter and the pulse generator;

a pulse stretcher that receives an output of the exclusive-OR gate;

an AND gate that receives an output of the pulse stretcher and a clock signal on each of its inputs;

a flip-flop that receives the output of the pulse generator on an input and the output of the exclusive-OR gate on its clock input;

a counter comprising an up/down input for indicating whether the counter counts up or down and is attached to an output of the flip-flop, a clock input attached to the AND gate output, and a clear input attached to a control circuit, the counter further comprising N parallel outputs;

a latch comprising N parallel input and connected to the N parallel outputs of the counter and further comprising a clock input attached to an output of the control circuit and N parallel outputs; and

wherein the control circuit clocks the data from the counter to the latch on the positive transition of the intermediate frequency signal frequency signal, and sequentially clears the counter.

7. The device of claim 6 further comprising a digital signal processor for receiving the N parallel outputs of the latch.

8. The device of claim 6 further comprising a digital to analog converter for receiving the N parallel outputs of the latch and a base band amplifier for amplifying an output of the digital to analog converter.

9. The device of claim 6 further comprising an accumulator and an accumulator latch interposed between the counter and the latch for receiving the N parallel outputs of the counter, the N parallel outputs of the accumulator latch to generate N parallel inputs to the second accumulator input port, and the latch receives the N parallel outputs of the accumulator latch.

10. The device of claim 6 wherein the pulse stretcher circuit comprises:

a first switch that receives the input of the pulse stretcher and outputs a reference voltage to an input of a variable dual slope integrator when the input is a positive voltage;

an analog to logic level converter receives the output of the integrator and generates the output of the pulse stretcher;

a pulse stretcher control receives the input of the pulse stretcher and the output of the analog to logic converter and outputs a positive voltage to a second switch when it detects a logical one to logical zero transition on the input of the pulse stretcher and sends a signal to a control input of the second switch;

the second switch outputs the reference voltage divided by N to a negative input of the variable dual slope integrator while the input of the second switch receives the signal from the accumulator control.

11. The device of claim 1 wherein the narrow band discriminator circuit comprises:

an analog to logic level converter for receiving the reduced deviation modulated signal;

a pulse generator that generates pulses with a fixed duration of one half the center frequency period of the intermediate frequency signal;

an exclusive-OR gate that receives an output of the logic level converter and the pulse generator;

a pulse stretcher that receives an output of the exclusive-OR gate;

an AND gate that receives an output of the pulse stretcher and a clock signal on each of its inputs;

a flip-flop that receives the output of the pulse generator on an input and the output of the exclusive-OR gate on its clock input;

a counter comprising a clock input attached to the AND gate output and a clear input attached to a control circuit, the counter further comprising N parallel outputs;

an accumulator and an accumulator latch interposed between the counter and the latch for receiving the N parallel outputs of the counter, adding or subtracting the N parallel outputs of the counter based upon the output of the flip-flop received on the accumulator'"'"'s plus/minus input to generate N parallel outputs to the accumulator latch;

a latch comprising N parallel inputs and connected to the N parallel outputs of the accumulator latch and further comprising a clock input attached to an output of the control circuit and N parallel outputs; and

wherein the control circuit clocks the data from the counter to the latch on the positive transition of the intermediate frequency signal, and sequentially clears the counter.

12. The device of claim 11 further comprising a digital signal processor for receiving the N parallel outputs of the latch.

13. The device of claim 11 further comprising a digital to analog converter for receiving the N parallel outputs of the latch and a base band amplifier for amplifying an output of the digital to analog converter.

14. The device of claim 11 wherein the pulse stretcher circuit comprises:

a first switch that receives the input of the pulse stretcher and outputs a reference voltage to an input of a variable dual slope integrator when the input is a positive voltage;

an analog to logic level converter receives the output of the integrator and generates the output of the pulse stretcher;

a pulse stretcher control receives the input of the pulse stretcher and the output of the analog to logic converter and outputs a positive voltage to a second switch when it detects a logical one to logical zero transition on the input of the pulse stretcher and sends a signal to a control input of the second switch;

the second switch outputs the reference voltage divided by N to a negative input of the variable dual slope integrator while the input of the second switch receives the signal from the accumulator control.

15. The device of claim 1 wherein the narrow band discriminator circuit comprises:

an analog to logic level converter for receiving the reduced deviation modulated signal;

a pulse generator that generates pulses with a fixed duration of one half the center frequency period of the intermediate frequency signal minus the time delay of the maximum frequency deviation;

an exclusive-OR gate that receives an output of the logic level converter and the pulse generator;

an AND gate that receives an output of the exclusive-OR gate and a clock signal on each of its inputs;

a counter comprising a clock input attached to the AND gate output and a clear input attached to a control circuit, the counter further comprising N parallel outputs;

a latch comprising N parallel input and connected to the N parallel outputs of the counter and further comprising a clock input attached to an output of the control circuit and N parallel outputs; and

wherein the control circuit clocks the data from the counter to the latch on the positive transition of the intermediate frequency signal

16. The device of claim 15 further comprising a digital signal processor for receiving the N parallel outputs of the latch.

17. The device of claim 15 further comprising a digital to analog converter for receiving the N parallel outputs of the latch and a base band amplifier for amplifying an output of the digital to analog converter.

18. The device of claim 15 further comprising an accumulator and an accumulator latch interposed between the counter and the latch for receiving the N parallel outputs of the counter, adding the N parallel outputs of the counter to the N parallel outputs of the accumulator latch to generate N parallel outputs to the accumulator latch and the latch receives the N parallel outputs of the accumulator latch.

19. The device of claim 1 wherein the narrow band discriminator circuit comprises:

an analog to logic level converter for receiving the reduced deviation modulated signal;

a pulse generator that generates pulses with a fixed duration of one half the center frequency period of the intermediate frequency signal;

an exclusive-OR gate that receives an output of the logic level converter and the pulse generator;

a flip-flop having an input connected to the pulse generator, a clock input connected to the output of the exclusive-OR gate, an output and a NOT output;

a first switch for receiving the output of the exclusive-OR gate and the output of the flip-flop and passing the flip-flop output when the output of the exclusive-OR gate is positive;

a second switch for receiving the output of the exclusive-OR gate and the NOT output of the flip-flop and passing the flip-flop output when the output of the exclusive-OR gate is negative;

a integrator having a positive input connected to the first switch and a negative input connected to the second switch; and

a low pass filter connected to the output of the integrator.

20. The device of claim 19 further comprising a pulse stretcher interposed between the connections of the exclusive-OR gate and the first and second switches.

21. The device of claim 1 wherein the narrow band discriminator circuit comprises:

an analog to logic level converter for receiving the reduced deviation modulated signal;

a pulse generator that generates pulses with a fixed duration of one half the center frequency period of the intermediate frequency signal minus the time delay of the maximum frequency deviation;

an exclusive-OR gate having an input attached to the output of the analog to logic level converter and an input attached to the output of the pulse generator; and

a low pass filter attached to the output of the exclusive-OR gate.

22. The device of claim 21 further comprising a pulse stretcher interposed between the exclusive-OR gate and the low pass filter.