Bus system and bus interface

• US 20030101298A1
• Filed: 09/24/2002
• Published: 05/29/2003
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Zhang, Zhenyu, Chang, Yeow Khai
• Granted Patent: US 7,043,589 B2
• Time in Patent Office: Days
• US Class Current: 710/107
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus

Abstract

The invention relates to a bus system comprising a first station (202) and a second station (203, 204) coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station (202) repeatedly sends requests to said second station (203, 204) and the second station responds to the requests. The first station (202) comprises an interruptible processor (206) and a bus interface (207). The bus interface (207) is operable to interrupt the interruptible processor (206) upon reception of selected responses of the second station (203, 204). The interruptible processor (206) is operable to handle the interrupts of the bus interface (207).

Claims

1. A bus system comprising a first station (202) and a second station (203, 204) coupled by a bus for transferring data and control signals, said bus operating according to a protocol in which said first station (202) repeatedly sends requests to said second station (203, 204) and said second station (203, 204) responds to said requests, characterized in that said first station (202) comprises an interruptible processor (206) and a bus interface (207), where

said bus interface (207) is operable for interrupting said interruptible processor (206) upon reception of selected responses of said second station (203, 204), and

said interruptible processor (206) is operable to handle the interrupts of said bus interface (207).

2. A bus system as claimed in claim 1, characterized in that said selected responses comprise the absence of a response signal from the second station.

3. A bus system as claimed in claim 1, characterized in that said bus system is a USB bus system.

4. A bus interface comprising a connection for a bus (403) and an interrupt output for applying an interrupt to an interruptible processor, characterized in that said bus interface also comprises a controller (409) operable to receive responses from said connection (403) and to interrupt said processor upon reception of selected responses by sending an interrupt signal to the interrupt output.

5. A bus interface as claimed in claim 4, characterized in that said selected responses comprise the absence of a response signal on said connection.

6. A bus interface for connection to a bus as claimed in claim 4, characterized in that said station is arranged to operate as a USB interface.