Multiple virtual machine environment management system

• US 20030101440A1
• Filed: 05/29/2002
• Published: 05/29/2003
• Est. Priority Date: 01/17/2001
• Status: Abandoned Application

• Current Assignee: aJile Systems, Inc.
• Original Assignee: aJile Systems, Inc.
• Inventors: Masters, Michael H., Hardin, David S., Mass, Allen P., Mykris, Nick M.
• Application Number:
  US10/157,005
• Publication Number:
  US 20030101440A1
• Time in Patent Office: Days
• US Class Current: 717/148
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An apparatus and method of running multiple concurrent virtual machines is disclosed. A memory component, a timer component, a multiple virtual machine control component, and a processor component can be included. The timer component can include a virtual machine activation period timer and a plurality of virtual machine dedicated timers. The processor component can process instructions of a virtual machine indicated to be the active virtual machine. The processor component can suspend processing instructions of a virtual machine when the virtual machine activation period timer causes the timer component to indicate a virtual machine switch. A memory protection component and process can also be included.

Claims

1. An apparatus capable of running multiple concurrent virtual machines, comprising:

a memory component storing a plurality of virtual machine specific memory content sets, each virtual machine specific memory content set of said plurality of virtual machine specific memory content sets defining a distinct virtual machine such that the plurality of virtual machine specific memory content sets define a plurality of virtual machines, each virtual machine having an active period wherein its instructions are executed;

a timer component, comprising;

a virtual machine activation period timer, said virtual machine activation period timer timing an activated virtual machine'"'"'s active period,

a plurality of virtual machine dedicated timers, each virtual machine dedicated timer dedicated to timing an interval of interest to the specific virtual machine to which it is dedicated, and

an active virtual machine switch signal output;

a multiple virtual machine control component, comprising an active virtual machine identification signal output, said multiple virtual machine control component being capable of determining which virtual machine of the plurality of virtual machines should be the active virtual machine; and

a processor component, communicatively coupled with said timer component, said processor component being capable of processing instructions of a virtual machine indicated by said active virtual machine identification signal output to be the active virtual machine;

wherein said processor component suspends processing instructions of a virtual machine when the virtual machine activation period timer causes said timer component to indicate a virtual machine switch via said active virtual machine switch signal output.

2. The apparatus of claim 1, wherein at least one virtual machine dedicated timer of said plurality of virtual machine dedicated timers comprises a piano roll timer.

3. The apparatus of claim 2, further comprising an interrupt control component, and wherein said timer component further comprises a piano roll timer output signal coupled with said interrupt control component.

4. The apparatus of claim 2, wherein at least one virtual machine dedicated timer of said plurality of virtual machine dedicated timers comprises a general-purpose timer.

5. The apparatus of claim 4, further comprising an interrupt control component, and wherein said timer component further comprises a general-purpose timer output signal coupled with said interrupt control component.

6. The apparatus of claim 4, further comprising an interrupt control component, and wherein said timer component further comprises a piano roll timer output signal coupled with said interrupt control component and a general purpose timer output signal coupled with said interrupt control component.

7. The apparatus of claim 1, further comprising an interrupt controller component communicatively coupled with said processor component and said timer component.

8. The apparatus of claim 7, wherein said interrupt controller component comprises a detected interrupt signal output coupled with said processor component.

9. The apparatus of claim 1, wherein said multiple virtual machine control component further comprises a memory protection mode indication signal output.

10. The apparatus of claim 9, further comprising an external bus interface component coupled with said virtual machine identification signal output and with said memory protection mode indication output.

11. The apparatus of claim 10, further comprising a trusted mode indication signal line coupling said processor component with said external bus interface component such that said processor component can output a trusted mode indication signal to said external bus interface component.

12. The apparatus of claim 10, further comprising a memory protection device coupled with said external bus interface.

13. The apparatus of claim 12, wherein said memory protection device comprises a programmable logic device.

14. The apparatus of claim 1, wherein said processor component comprises a processor capable of directly executing JAVA bytecodes.

15. The apparatus of claim 1, further comprising a single chip substrate, and wherein said timer component, said multiple virtual machine control component and said processor component are all located on said single chip substrate.

16. The apparatus of claim 15, further comprising an interrupt controller component communicatively coupled with said processor component, said interrupt controller component located on said single chip substrate.

17. The apparatus of claim 16, further comprising an external bus interface component, said external bus interface component located on said single chip substrate, and said external bus interface component being coupled with each of said processor component, said multiple virtual machine control component and said interrupt controller component.

18. The apparatus of claim 17, further comprising a processor bus;

said processor component, said multiple virtual machine control component and said external bus interface component each coupled with said processor bus.

19. The apparatus of claim 18, further comprising a peripheral bus, said peripheral bus coupled with said external bus interface component, said peripheral bus located on said single chip substrate.

20. The apparatus of claim 19, further comprising a peripheral bus bridge, said peripheral bus bridge coupling said peripheral bus to said processor bus.

21. The apparatus of claim 17, further comprising a memory protection device, said memory protection device located on a substrate other than said single chip substrate, said memory protection device coupled with said external bus interface component.

22. The apparatus of claim 21, wherein said memory protection device comprises a programmable logic device.

23. The apparatus of claim 15, further comprising a memory protection device, said memory protection device located on said single chip substrate.

24. A multiple virtual machine management apparatus, comprising:

a memory protection component comprising an active virtual machine identification input, a memory access location input, and a memory access error output; and

an integrated circuit chip, comprising;

a processor component;

a multiple virtual machine management component coupled with said processor component, said multiple virtual machine management component comprising a virtual machine activation period timer and a plurality of virtual machine dedicated timers;

a memory access error input coupled with memory access error output;

an active virtual machine identification output coupled with said active virtual machine identification input; and

a memory access location output coupled with said memory access location input;

wherein said memory protection component indicates a memory access error via said memory access error output when said memory access location input indicates a memory location not associated with a virtual machine identified by said active virtual machine identification output.

25. The multiple virtual machine management apparatus of claim 24, wherein at least one virtual machine dedicated timer of said plurality of virtual machine dedicated timers comprises a piano roll timer.

26. The multiple virtual machine management apparatus of claim 25, further comprising an interrupt control component, and wherein said timer component further comprises a piano roll timer output signal coupled with said interrupt control component.

27. The multiple virtual machine management apparatus of claim 25, wherein at least one virtual machine dedicated timer of said plurality of virtual machine dedicated timers comprises a general purpose timer.

28. The multiple virtual machine management apparatus of claim 27, further comprising an interrupt control component, and wherein said timer component further comprises a general-purpose timer output signal coupled with said interrupt control component.

29. The multiple virtual machine management apparatus of claim 27, further comprising an interrupt control component, and wherein said timer component further comprises a piano roll timer output signal coupled with said interrupt control component and a general purpose timer output signal coupled with said interrupt control component.

30. The multiple virtual machine management apparatus of claim 24, further comprising a plurality of memory components communicatively coupled with said integrated circuit chip, and wherein said memory access location output identifies a specific memory component of said plurality of memory components.

31. The multiple virtual machine management apparatus of claim 24, further comprising a memory component communicatively coupled with said integrated circuit chip, and wherein said memory access location output identifies a specific memory address in said memory component.

32. A method for managing a system running a plurality of virtual machines, comprising the steps of:

selecting, from a plurality of virtual machines, a virtual machine to be activated;

activating the selected virtual machine;

timing the activation period of the activated virtual machine;

running a virtual machine specific timer that is dedicated to the virtual machine that is currently activated, to time an interval of interest to its related virtual machine;

executing code, during said timing step, associated with the activated virtual machine;

communicating the identity of the activated virtual machine to other components;

indicating the expiration of the interval of interest timed by the virtual machine specific timer; and

signaling, upon completion of said timing step, the end of the activated virtual machine'"'"'s activation period.

33. The method of claim 32, wherein the virtual machine specific timer of said running step is used as a piano roll timer.

34. The method of claim 32, wherein the virtual machine specific timer of said running step is used as a general-purpose timer.

35. The method of claim 32, wherein the virtual machine specific timer of said running step is used as a general purpose timer;

and further comprising the step of starting a piano roll timer during said timing step.

36. The method of claim 32, wherein said running step further comprises the running of an additional virtual machine specific timer.

37. The method of claim 32, wherein said running step further comprises the running of a plurality of virtual machine specific timers.

38. The method of claim 32, further comprising the step of starting an additional virtual machine specific timer during said timing step.

39. The method of claim 38, wherein the virtual machine specific timer of said running step is used as a piano roll timer, and wherein the additional virtual machine specific timer of said starting step is used as a general purpose timer.

40. The method of claim 32, further comprising the step of asserting a trusted mode indication signal.

41. The method of claim 32, further comprising the step of asserting an untrusted mode indication signal.

42. The method of claim 32, further comprising the step of asserting a memory protection mode indication signal.

43. The method of claim 32, wherein said signaling step comprises the step of sending a switch interrupt signal to an interrupt controller.

44. The method of claim 32, wherein said activating step comprises activating a Java virtual machine.

45. The method of claim 32, wherein said selecting step is accomplished by following an activation schedule.

46. The method of claim 32, wherein said timing step comprises the step of running the timer dedicated to the activated virtual machine for a predetermined activation period.

47. The method of claim 32, further comprising the step of assigning a memory region to at least one virtual machine of the plurality of virtual machines.

48. The method of claim 47, further comprising the step of protecting a virtual machine'"'"'s assigned memory region from being accessed by a different virtual machine.

49. The method of claim 48, wherein said protecting step further comprises the steps of:

screening a memory access; and

generating an abort interrupt signal to abort an access to a memory region of a non-activated virtual machine.

50. The method of claim 48, further comprising the step of outputting the identity of the activated virtual machine to a memory management component.

51. The method of claim 50, further comprising the step of defining, by the memory management component, the memory region assigned to the activated virtual machine.

52. The method of claim 51, further comprising the step of monitoring address lines to abort attempted memory accesses to a protected memory region.

53. The method of claim 52, further comprising the step of aborting an attempted access of a protected memory region by generating an error signal.

54. The method of claim 52, further comprising the step of aborting an attempted access of a protected memory region by generating a prioritized non-maskable interrupt signal.

55. The method of claim 52, further comprising the step of aborting an attempted access of a protected memory region by generating a highest priority prioritized non-maskable interrupt signal.

56. An apparatus, comprising:

means for storing a plurality of virtual machine specific memory content sets, each virtual machine specific memory content set of said plurality of virtual machine specific memory content sets defining a distinct virtual machine such that the plurality of virtual machine specific memory content sets define a plurality of virtual machines, each virtual machine having an active period wherein its instructions are executed;

a plurality of means for timing, at least one said means for timing being dedicated to time the active period of an activated virtual machine, and at least one said means for timing being dedicated to time an interval related to a specific virtual machine;

means for determining which virtual machine should be the active virtual machine; and

means for processing, communicatively coupled with said plurality of means for timing, said means for processing being capable of processing instructions of a virtual machine indicated by said means for determining to be the active virtual machine;

wherein said means for processing suspends processing instructions of a virtual machine when the end of a virtual machine'"'"'s active period is indicated by said at least one means for timing that is dedicated to time the active period.

57. The apparatus of claim 56, wherein said at least one means for timing that is dedicated to time a virtual machine specific interval is used as a piano roll timing device.