Method of joining components

• US 20030102079A1
• Filed: 01/06/2003
• Published: 06/05/2003
• Est. Priority Date: 01/17/2000
• Status: Active Grant

• Current Assignee: FAUN Data AB
• Original Assignee: Faun AB
• Inventors: Kalvesten, Edvard, Stemme, Goran, Niklaus, Frank
• Granted Patent: US 7,067,345 B2
• Time in Patent Office: Days
• US Class Current: 156/299
• CPC Class Codes: G01J 5/02 Constructional details
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01072 Hafnium [Hf]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: Y10T 156/1092 : All laminae planar and face to face

Abstract

A method of combining components to form an integrated device, wherein the components are provided on a first sacrificial wafer, and a second non-sacrificial wafer, respectively. The sacrificial wafer carries a first plurality of components and the non-sacrificial wafer carries a second plurality of components. The wafers are bonded together with an intermediate bonding material. Optionally the sacrificial wafer is thinned to a desired level. The components of the sacrificial wafer are electrically interconnected to the component(s) on the non-sacrificial wafer. Finally, optionally the intermediate bonding material is stripped away.

Claims

1. A method of combining components to form an integrated device, wherein said components are provided on a first sacrificial substrate, and a second non-sacrificial substrate, respectively, comprising the following steps:

bonding said sacrificial wafer carrying a first plurality of components, and said non-sacrificial substrate carrying a second plurality of components, respectively, with an intermediate bonding material;

optionally patterning and/or thinning said sacrificial substrate;

interconnecting the components of the sacrificial substrate with the components on the non-sacrificial substrate.

2. The metod of claim 1, further comprising stripping away the intermediate bonding material.

3. The method of claim 1, wherein the components on said sacrificial substrate are transducers, and the components on said non-sacrificial layer are electronic devices, such as readout devices (ROIC).

4. The method of claim 1, wherein said substrates are provided with contact pads for said electrical interconnection.

5. The method of claim 1, wherein said interconnection is an electrical interconnection, such as conducting material provided between said components.

6. The method of claim 1, wherein said intermediate bonding material is aa low temperature adhesive, e.g. a polymer selected from poly-imide, bensocyclobutene (BCB), epoxy, photoresist.

7. The method of claim 2, wherein said transducer is selected from the group consisting of IR detectors, RF devices and optical devices.

8. The method of claim 7, wherein the IR detectors are selected from the group consisitng of a bolometer, a quantum well detector, and a pyroelectric detector.

9. The method of claim 1, wherein said bonding is performed by bringing the substrates together and exerting a pressure and optionally applying an elevated temperature thereto.

10. The method of claim 1, wherein said thinning of the sacrificial substrate is performed by mechanical means or by etching away part of or the entire substrate.

11. The method of claim 1, wherein said intermediate bonding is performed by providing said intermediate bonding material on at least one of said substrates.

12. The method of claim 11, wherein said intermediate bonding is provided only on parts of said substrate(s).

13. The method of claim 1, wherein said first and second micro electronic structures have at least one contact point each between which it is desired to establish said interconnection.

14. The method of claim 13, wherin portions of said intermediate polymer layer are

selectively removed such that said contact points are exposed.