Semiconductor device and method for manufacturing

• US 20030102551A1
• Filed: 12/31/2002
• Published: 06/05/2003
• Est. Priority Date: 07/13/2000
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Kikuchi, Hidekazu
• Granted Patent: US 7,586,181 B2
• Time in Patent Office: Days
• US Class Current: 257/701
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device which has trenches for raising the reliability thereof and a method for manufacturing such device. An electrode pad, and a protective film and an interlayer film which comprise an opening on top of this electrode pad, are formed on a substrate. A rewiring pattern which is in contact with the electrode pad at this opening is formed on top of the interlayer film. In addition, a trench is formed, by means of etching, in the region on this interlayer film where said rewiring pattern is not formed. A bump is formed on top of said rewiring pattern. The rewiring pattern and the trench are covered by means of a sealing film. The sealing film exposes the upper end of the bump. An external terminal is formed on the upper end of this bump. The trenches make the contact area between the covering film and the sealing film larger and therefore increase the adhesion between the covering film and the sealing film. The rougher the surface of the trench the better the adhesion between the covering film and the sealing film. Improving the adhesion makes it difficult for the sealing film to become detached so that the semiconductor device becomes more reliable.

Claims

1. A semiconductor device, comprising:

an electrode pad which is formed on a substrate;

a covering film which is formed on said substrate and comprises an opening on top of said electrode pad;

a rewiring pattern which is formed on said covering film and makes contact with said electrode pad at said opening;

a trench which is formed in the region of the interlayer film where said rewiring pattern is not formed;

a bump which is formed on top of said rewiring pattern; and

a sealing film which covers said rewiring pattern and said trench, and is formed in such a way that the upper end of the bump is exposed.

2. The semiconductor device according to claim 1, wherein said covering film comprises a protective film which is formed on top of said substrate and comprises a first opening on top of said electrode pad, and an interlayer film which is formed on top of said protective film and comprises a second opening on top of said electrode pad.

3. The semiconductor device according to claim 2, wherein said interlayer film has a modifying layer for improving the adhesion of the interlayer film with respect to said rewiring pattern.

4. The semiconductor device according to claim 3, wherein said modifying film is segmented at each of said rewiring patterns by means of said trench.

5. The semiconductor device according to claim 2, wherein said protective film is exposed at the bottom surface of said trench.

6. The semiconductor device according to claim 1, wherein said trench is formed by means of wet etching.

7. The semiconductor device according to claim 1, wherein said trench is formed by means of anisotropic etching.

8. The semiconductor device according to claim 7, wherein said anisotropic etching is plasma etching.

9. The semiconductor device according to claim 2, wherein said second opening in said interlayer film is formed in such a way that it exposes the side face of said first opening in said protective film.

10. The semiconductor device according to claim 1, wherein said rewiring pattern comprises a highly conductive wiring layer, and an adhesive layer for improving the adhesion of this rewiring pattern with respect to said covering layer.

11. The semiconductor device according to claim 1, further comprising an external terminal which is formed on top of said bump.

12. The semiconductor device according to claim 1, wherein said device is formed by means of a wafer level chip size package method.

13. A method for manufacturing a semiconductor device comprising steps of:

forming an electrode pad on top of a substrate;

forming, on top of said substrate, a covering film which comprises an opening on top of said electrode pad;

forming, on top of said covering film, a rewiring pattern which is in contact with said electrode pad at said opening;

forming a trench in the region of said covering film where said rewiring pattern is not formed;

forming a bump on top of said rewiring pattern; and

forming a sealing film which covers said rewiring pattern and said trench, in such a way that said sealing film exposes the upper end of said bump.

14. The method for manufacturing a semiconductor device according to claim 13, wherein said step of forming a covering film comprises steps of:

forming, on top of said substrate, a protective film which comprises a first opening on top of said electrode pad; and

forming, on top of said protective layer, an interlayer film which comprises a second opening on top of said electrode pad.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising a step of forming, on the surface of said interlayer film, a modifying layer for improving the adhesion of the interlayer film with respect to said rewiring pattern.

16. The method for manufacturing a semiconductor device according to claim 15 wherein said step of forming a modifying layer comprises a step of performing plasma processing on the surface of said interlayer film.

17. The method for manufacturing a semiconductor device according to claim 13, wherein said step of forming a rewiring pattern comprises steps of:

forming an metallic thin film for improving the adhesion of this rewiring pattern with respect to said covering film, and

forming metallic wiring on the surface of said metallic thin film.

18. The method for manufacturing a semiconductor device according to claim 15, wherein said modifying layer is segmented at each rewiring pattern by means of said step of forming a trench.

19. The method for manufacturing a semiconductor device according to claim 13, wherein said step of forming a trench comprises a wet etching process.

20. The method for manufacturing a semiconductor device according to claim 13, wherein said step of forming a trench comprises an anisotropic etching process.

21. The method for manufacturing a semiconductor device according to claim 20, wherein said anisotropic etching is plasma etching.

22. The method for manufacturing a semiconductor device according to claim 14, wherein said step of forming a trench is the same step as a step of providing a second opening in said interlayer film.

23. The method for manufacturing a semiconductor device according to claim 14, wherein said step of forming a trench is a step of forming a trench with a depth which causes said protective film to be exposed.

24. The method for manufacturing a semiconductor device according to claim 14, wherein said step of forming an interlayer film includes a step of forming said second opening so that the side face of said first opening of said protective film is exposed.

25. The method for manufacturing a semiconductor device according to claim 13 further comprising a step of forming an external terminal on top of said bump.

26. The method for manufacturing a semiconductor device according to claim 13, wherein said semiconductor device is manufactured by means of a wafer level chip size package method.