Semiconductor memory device reading data based on memory cell passing current during access

• US 20030103395A1
• Filed: 06/04/2002
• Published: 06/05/2003
• Est. Priority Date: 12/03/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Granted Patent: US 6,791,890 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

A data read circuit produces read data in accordance with a difference between currents flowing through first and second nodes, respectively. In a data read operation, a current transmitting circuit and a reference current generating circuit pass an access current corresponding to a passing current of a selected memory cell and a predetermined reference current through first and second nodes, respectively. In a test mode, a current switching circuit passes equal test currents through the first and second nodes instead of the access current and the reference current, respectively. Thereby, offset of the current sense amplifier in the data read circuit can be evaluated.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells each having passing current changing in accordance with storage data during access;

an access current transmitting circuit for passing, to a first node, an access current corresponding to said passing current of a selected memory cell selected from said plurality of memory cells as an access target;

a reference current generating circuit for passing a reference current to a second node during data reading;

a current comparing circuit for producing a read voltage corresponding to a difference between currents flowing through said first and second nodes, respectively; and

a test current supply circuit for supplying an externally test current to at least one of said first and second nodes in a test mode.

2. The semiconductor memory device according to claim 1, further comprising

an offset detecting circuit for evaluating offset occurring in said current comparing circuit based on said read voltage in said test mode, wherein

said test current supply circuit supplies said test currents to each of said first and second nodes in said test mode.

3. The semiconductor memory device according to claim 2, wherein

said offset detecting circuit detects in said test mode whether said read voltage falls within a predetermined range or not.

4. The semiconductor memory device according to claim 2, wherein

each of said memory cells is designed to have one of a first electric resistance and a second electric resistance larger than said first electric resistance in accordance with the level of said storage data, and

said access current transmitting circuit includes a transmission switch portion for electrically coupling said first node to a third node connected to said selected memory cell and passing said passing current based on a comparison made between the voltage on said third node and a reference voltage.

5. The semiconductor memory device according to claim 2, wherein

said current comparing circuit includes:

a first impedance tuning circuit for tuning an input impedance to said first node in accordance with a first control signal, and

a second impedance tuning circuit for tuning an input impedance to a second node in accordance with a second control signal different from said first control signal.

6. The semiconductor memory device according to claim 5, further comprising:

a decode circuit for producing said first and second control signals in accordance with an externally applied test input in said test mode;

a memory portion for storing said first and second control signals to be used in a normal operation; and

a selector circuit for selectively transmitting said first and second control signals from one of said decode circuit and said memory portion to said current comparing circuit, wherein

said first and second control signals stored in said memory portion are set corresponding to said test input applied when said offset of said current comparing circuit is smaller than a predetermined level in said test mode.

7. The semiconductor memory device according to claim 1, further comprising

a current detecting circuit for detecting a relationship in magnitude of one of said access current and said reference current with said test current based on said read voltage in said test mode, wherein

said test current supply circuit supplies said test currents to one of said first and second nodes, instead of one of said access current and said reference current, in said test mode.

8. The semiconductor memory device according to claim 7, wherein

said reference current generating circuit includes:

a dummy memory cell for passing therethrough a current intermediate between two kinds of the passing currents corresponding to two kinds of levels of said storage data in each of said memory cells, respectively,

a current transmitting circuit for transmitting the current passing through said dummy memory cell to a third node, and

a current generating circuit for generating said reference current in accordance with a current flowing through said third node; and

said current transmitting circuit has an input impedance tuned in accordance with a control signal.

9. A semiconductor memory device comprising:

a plurality of memory cells each for holding storage data;

a first node, in a read operation, being electrically connected to a selected memory cell selected from said plurality of memory cells as an access target;

a second node for transmitting a electric reference signal in order to be compared with a electric signal transmitted by said first node, in said read operation;

a data read circuit for outputting a read voltage according to a difference between the electric signals of said first and second nodes in said data read operation; and

an offset tuning circuit for tuning input impedance of said first and second nodes in accordance with first and second control voltages obtained by feedback of said read voltage so as to keep said read voltage within a predetermined range when said data read operation is inactive.

10. The semiconductor memory device according to claim 9, wherein

said data read circuit outputs said read voltage corresponding to a voltage difference between said first and second nodes in said data read operation, and

said semiconductor memory device further comprises:

a voltage holding circuit for holding said first and second control voltages; and

a switch circuit for interrupting a feedback path of said read voltage in said data read operation.

11. The semiconductor memory device according to claim 10, further comprising:

an offset tuning circuit for applying equal voltages to said first and second nodes, respectively, during a period other than said data read operation.

12. The semiconductor memory device according to claim 9, wherein

each of said plurality of memory cells has passing current changing in accordance with said storage data during access;

and

said semiconductor memory device according further comprises;

an access current transmitting circuit for passing, to said first node, an access current corresponding to said passing current of said selected memory cell;

a reference current generating circuit for passing a reference current to said second node as said electric reference signal in said data read operation; and

a current switching circuit for carrying said reference current instead of said access current to said first node when said data read operation is inactive;

wherein

said data write circuit outputs said read voltage according to a difference between currents flowing through said first and second nodes, respectively.

13. The semiconductor memory device according to claim 12, further comprising:

a voltage holding circuit for holding said first and second control voltages, and

a switch circuit for interrupting a feedback path of said read voltage in said data read operation.

14. The semiconductor memory device according to claim 12, wherein

said offset tuning circuit includes:

a first tuning current generating circuit for carrying a current corresponding to said first control voltage into or from said first node, and

a second tuning current generating circuit for carrying a current corresponding to said second control voltage into or from said second node.

15. A semiconductor memory device comprising:

a plurality of memory cells each having passing current changing in accordance with storage data during access;

an access current transmitting circuit for passing an access current depending on said passing current to a first node, based on a comparison between a reference voltage and a voltage on an internal node passing said passing current therethrough and connected to the selected memory cell selected as an access target from said plurality of memory cells;

a reference current generating circuit for passing a reference current to a second node during data reading;

a current comparing circuit for producing a read voltage corresponding to a difference between the currents flowing through said first and second nodes, respectively; and

a reference current tuning circuit for tuning a level of said reference voltage in accordance with a result of manufacturing of each of said memory cells.

16. The semiconductor memory device according to claim 15, wherein

said reference current tuning circuit includes:

a dummy memory cell formed on said semiconductor memory device, and having a structure similar to that of each of said memory cells, and

a voltage tuning circuit for tuning a level of said reference voltage in accordance with a passing current of said dummy memory cell.

17. A semiconductor memory device comprising:

a plurality of memory cells each having passing current changing in accordance with storage data during access;

an access current transmitting circuit for passing, to a first node, an access current corresponding to said passing current of the selected memory cell selected from said plurality of memory cells as an access target; and

a reference current generating circuit for passing a reference current to a second node during data reading,

said reference current generating circuit including;

a plurality of dummy memory cells formed on said semiconductor memory device, and each having a structure similar to that of said memory cell, and

a current generating circuit for generating said reference current based on the passing currents of said plurality of dummy memory cells;

wherein

at least one of said plurality of dummy memory cells store one of two kinds of levels of said storage data, and at least another one of said memory cells store the other of said two kinds of levels of said storage data; and

said semiconductor memory device further comprising

a current comparing circuit for producing a read voltage corresponding to a difference between currents flowing through said first and second nodes, respectively.

18. The semiconductor memory device according to claim 17, wherein

said current generating circuit generates said reference current in accordance with an average value of the passing currents of the dummy memory storing said one of said two kinds of levels and the passing currents of the dummy cells storing said the other of said two kinds of levels.