Multistage autozero sensing for a multilevel non-volatile memory integrated circuit system

• US 20030103400A1
• Filed: 12/11/2002
• Published: 06/05/2003
• Est. Priority Date: 01/14/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Van Tran, Hieu
• Granted Patent: US 6,956,779 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.

Claims

1. A sense amplifier comprising:

a first switch to selectively couple a data cell or a reference cell to a first node;

a current generator coupled to the first node to provide a current indicative of a voltage on the first node;

a comparison circuit having a first input coupled to the first node, having a second terminal coupled to a second node, and having an output terminal to generate an output signal indicative of the difference between the voltages on the first and second node; and

a second switch coupled between the output terminal and the second node to set the voltage of the second node to a voltage indicative of the voltage on the first node in response to the first switch selectively coupling the reference cell to the first node.

2. The sense amplifier of claim 1 wherein the reference cell is a multilevel reference cell.

3. The sense amplifier of claim 1 wherein the data cell and the reference cell are nonvolatile cells.

4. The sense amplifier of claim 1 further comprising a replica loading circuit to load similarly an input of the first switch coupled to the data cell as loading of an input of the first switch coupled to the reference cell in response to the first switch selectively coupling the reference cell to the first node.

5. A sense amplifier comprising:

a first transistor of a first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel;

a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel;

a second transistor of the second type including a first terminal coupled to the first terminal of the first transistor of the second type, including a second terminal spaced apart from said first terminal of the second transistor of the second type with a channel therebetween and coupled to the gate of the first transistor of the first type, and including a gate for controlling the current in said channel in response to a first selection signal;

a second transistor of the first type including a first terminal coupled to the first terminal of the first transistor of the first type, including a second terminal spaced apart from the first terminal of the second transistor of the first type with a channel therebetween and coupled to the gate of the first transistor of the first type, and including a gate for controlling a current in said channel and coupled to said second terminal;

a third transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a reference memory cell terminal, and including a gate for controlling current in said channel in response to said first selection signal; and

a fourth transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a data memory cell terminal, and including a gate for controlling current in said channel in response to a second selection signal.

6. The sense amplifier of claim 5 wherein the reference memory cell terminal is to be coupled to a multilevel reference memory cell.

7. The sense amplifier of claim 5 further comprising a charge injection cancellation circuit coupled to the second terminal of the second transistor of the second type.

8. The sense amplifier of claim 7 wherein the charge injection cancellation circuit includes a capacitor coupled between the second terminal of the second transistor of the second type and the second selection signal.

9. The sense amplifier of claim 7 wherein the charge injection cancellation circuit comprises a third transistor of the first type including a first terminal coupled to the first terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal of the third transistor of the first type with a channel therebetween and coupled to the second terminal of the second transistor of the second type and including a gate for controlling a current in said channel in response to the first selection signal.

10. The sense amplifier of claim 5 further comprising a capacitor having a first terminal coupled to the gate of the first transistor of the second type and having a second terminal coupled to the ground terminal.

11. The sense amplifier of claim 5 further comprising:

a third transistor of the first type including a first terminal coupled to the first terminal of the third transistor of the second type, including a second terminal spaced apart from the first terminal of the third transistor of the first type with a channel therebetween and coupled to the second terminal of the third transistor of the second type, and including a gate for controlling the current in said channel in response to said second selection signal; and

a fourth transistor of the first type including a first terminal coupled to the first terminal of the fourth transistor of the second type, including a second terminal spaced apart from said first terminal of the fourth transistor of the first type with a channel therebetween and coupled to the second terminal of the fourth transistor of the second type, and including a gate for controlling current in said channel in response to said first selection signal.

12. The sense amplifier of claim 5 further comprising:

a third transistor of the first type including a first terminal coupled to the first terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal of the third transistor of the first type with a channel therebetween, and including a gate for controlling a current in said channel and coupled to said second terminal; and

a fifth transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second terminal of the third transistor of the second type, and including a gate for controlling current in said channel in response to the first selection signal.

13. The sense amplifier of claim 12 further comprising a charge injection cancellation circuit coupled to the second terminal of the second transistor of the second type.

14. The sense amplifier of claim 13 wherein the charge injection cancellation circuit includes a capacitor coupled between the second terminal of the second transistor of the second type and the second selection signal.

15. The sense amplifier of claim 13 wherein the charge injection cancellation circuit comprises a fourth transistor of the first type including a first terminal coupled to the first terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal of the fourth transistor of the first type with a channel therebetween and coupled to the second terminal of the second transistor of the second type, and including a gate for controlling a current in said channel in response to the second selection signal.

16. The sense amplifier of claim 12 further comprising a capacitor having a first terminal coupled to the gate of the first transistor of the second type and having a second terminal coupled to the ground terminal.

17. The sense amplifier of claim 12 further comprising:

a fourth transistor of the first type including a first terminal coupled to the first terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal of the fourth transistor of the first type with a channel therebetween, including a gate for controlling current in said channel and coupled to the gate of the first transistor of the first type;

a sixth transistor of the second type including a first terminal coupled to the second terminal of the fourth transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling a current in said channel and coupled to the second terminal of the first transistor of the first type; and

a seventh transistor of the second type including a first terminal coupled to the first terminal of the seventh transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate terminal of the seventh transistor of the second type, and including a gate for controlling current in said channel in response to said first selection signal.

18. The sense amplifier of claim 17 further comprising a first charge injection cancellation circuit coupled to the second terminal of the sixth transistor of the second type and a second charge injection cancellation circuit coupled to the second terminal of the first transistor of the second type.

19. The sense amplifier of claim 18 wherein the first charge injection cancellation circuit includes a capacitor coupled between the second terminal of the sixth transistor of the second type and the second selection signal, and a second charge injection cancellation circuit includes a capacitor coupled between the second terminal of the first transistor of the second type and the second selection signal.

20. The sense amplifier of claim 18 wherein the first charge injection cancellation circuit includes a fifth transistor of the first type including a first terminal coupled to the first terminal of the seventh transistor of the second type, including a second terminal spaced apart from said first terminal of the fifth transistor of the first type with a channel therebetween and coupled to the second terminal of the seventh transistor of the second type, and including a gate for controlling a current in said channel in response to said first selection signal, and the second charge injection cancellation circuit comprises a sixth transistor of the first type, including a first terminal coupled to the first terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal of the sixth transistor of the first type with a channel therebetween and coupled to the second terminal of the second transistor of the second type, and including a gate for controlling a current in said channel in response to said first selection signal.

21. The sense amplifier of claim 17 further comprising a capacitor coupling the common node formed of the second terminal of the first transistor of the first type and the first terminal of the first transistor of the second type to a common node formed of the gate of the sixth transistor of the second type and the second terminal of the seventh transistor of the second type.

22. The sense amplifier of claim 17 further comprising a first capacitor coupling the gate of the first transistor of the second type to the ground terminal, and comprising a second capacitor coupling the gate of the sixth transistor of the second type to the ground terminal.

23. The sense amplifier of claim 5 further comprising:

a third transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel;

a fifth transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the gate of the third transistor of the first type;

a sixth transistor of the second type including a first terminal coupled to the first terminal of the fifth transistor of the second type, including a second terminal spaced apart from said first terminal of the sixth transistor of the second type with a channel therebetween and coupled to the gate of said fifth transistor of the second type, and including a gate for controlling current in said channel in response to the first selection signal; and

a capacitor including a first terminal coupled to the gate of the sixth transistor of the second type and including a second terminal coupled to a common node formed of the second terminal of the first transistor of the first type and the first terminal of the first transistor of the second type.

24. The sense amplifier of claim 23 further comprising a first charge injection cancellation circuit coupled to the second terminal of the fifth transistor of the second type, and a second charge injection cancellation circuit coupled to the second terminal of the second transistor of the second type.

25. The sense amplifier of claim 24 wherein the first charge injection cancellation circuit includes the capacitor coupled between the second terminal of the fifth transistor of the second type and a second selection signal, and the second charge injection cancellation circuit includes the capacitor coupled between the second terminal of the second transistor of the second type and the second selection signal.

26. The sense amplifier of claim 24 wherein the first charge injection cancellation circuit comprises a fourth transistor of the first type including the first terminal coupled to the first terminal of the fifth transistor of the second type, including a second terminal spaced apart from said first terminal of the fourth transistor of the first type with a channel therebetween and coupled to the second terminal of the sixth transistor of the second type, and including a gate for controlling a current in said channel in response to the second selection signal, and

wherein the second charge injection cancellation circuit comprises a fifth transistor of the first type including a first terminal coupled to the first terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal of the fifth transistor of the first type with a channel therebetween and coupled to the second terminal of the second transistor of the second type, and including a gate for controlling a current in said channel in response to the second selection signal.

27. A sense amplifier comprising:

a storage device for storing a voltage;

a first switch circuit to selectively couple a data cell or a reference cell to the storage device in response to a selection signal being in a respective first or second state;

a comparison circuit having a first input coupled to the reference cell, having a second input coupled to the storage device, and having an output terminal to generate an output signal indicative of the difference between the voltages on the first and second inputs; and

a second switch circuit to selectively couple the second input of the comparison circuit to said output terminal in response to the selection signal being in said second state.

28. The sense amplifier of claim 27 wherein the reference cell is a multilevel reference cell.

29. The sense amplifier of claim 27 wherein the data cell and the reference cell are nonvolatile memory cells.

30. A sense amplifier comprising:

a first transistor of a first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel;

a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel;

a second transistor of the second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the second type, and including a gate for controlling current in said channel in response to a first selection signal;

a second transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to said second terminal;

a third transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to a reference cell terminal;

a fourth transistor of the second type including a first terminal coupled to the gate of the third transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal and including a gate for controlling current in said channel and coupled to said first terminal;

a fifth transistor of the second type including a first terminal coupled to the gate of the third transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel in response to said first selection signal;

a sixth transistor of the second type including a first terminal coupled to a data cell terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal;

a seventh transistor of the second type including a first terminal coupled to the data cell terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second terminal of the fifth transistor of the second type, and including a gate for controlling current in said channel in response to a second selection signal;

a capacitor including a first terminal coupled to the gate of said first transistor of the second type and including a second terminal coupled to the common node formed of the second terminals of the fifth and seventh transistors of the second type;

a third transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to an output terminal, including a gate for controlling current in said channel and coupled to the second terminal of the second transistor of the first type;

an eighth transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the second terminal of the first transistor of the first type; and

a ninth transistor of the second type including a first terminal coupled to the first terminal of the eighth transistor of the second type, including a second terminal spaced apart from the first terminal of the ninth transistor of the second type with a channel therebetween and coupled to the gate of the eighth transistor of the second type, and including a gate for controlling current in said channel in response to the first selection signal.

31. The sense amplifier of claim 30 further comprising a first charge injection cancellation circuit coupled to the second terminal of the second transistor of the second type and a second charge injection cancellation circuit coupled to the second terminal of the ninth transistor of the second type.

32. The sense amplifier of claim 31 wherein the first charge injection cancellation circuit includes a capacitor coupled between the second terminal of the second transistor of the second type and the second selection signal, and the second charge injection cancellation circuit includes a capacitor coupled between the second terminal of the ninth transistor of the second type and the second selection signal.

33. A sense amplifier comprising:

a storage device for storing a voltage;

a first switch circuit to selectively couple a data cell or a reference cell to the storage device in response to a selection signal being in a respective first or second state;

a comparison circuit having a first input coupled to the reference cell, having a second input coupled to the storage device, and having a first output terminal to generate a first output signal indicative of the difference between the voltages on the first and second inputs;

an output stage having an input capacitively coupled to the output terminal of the comparison circuit and having an output for providing a second output signal in response to the first output signal; and

a second switch circuit to selectively couple the second input of the comparison circuit to said first output terminal and to couple the first output terminal to the second output terminal in response to the selection signal being in said second state.

34. The sense amplifier of claim 33 wherein the reference cell is a multilevel reference cell.

35. The sense amplifier of claim 33 wherein the data cell and the reference cell are nonvolatile memory cells.

36. A sense amplifier comprising:

a first transistor of a first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel;

a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel;

a second transistor of the second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the second type, and including a gate for controlling current in said channel in response to a first selection signal;

a second transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to said second terminal;

a third transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to a reference cell terminal;

a fourth transistor of the second type including a first terminal coupled to the gate of the third transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal and including a gate for controlling current in said channel and coupled to said first terminal;

a fifth transistor of the second type including a first terminal coupled to the gate of the third transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel in response to said first selection signal;

a sixth transistor of the second type including a first terminal coupled to a data cell terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal;

a seventh transistor of the second type including a first terminal coupled to the data cell terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the second terminal of the fifth transistor of the second type, and including a gate for controlling current in said channel in response to a second selection signal;

a first capacitor including a first terminal coupled to the gate of said first transistor of the second type and including a second terminal coupled to the common node formed of the second terminals of the fifth and seventh transistors of the second type;

a third transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to an output terminal, and including a gate for controlling current in said channel;

an eighth transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the gate of the third transistor of the first type;

a ninth transistor of the second type including a first terminal coupled to the first terminal of the eighth transistor of the second type, including a second terminal spaced apart from the first terminal of the ninth transistor of the second type with a channel therebetween and coupled to the gate of the eighth transistor of the second type, and including a gate for controlling current in said channel in response to the first selection signal; and

a second capacitor including a first terminal coupled to the gates of the third transistor of the first type and the eighth transistor of the second type and including a second terminal coupled to the second terminal of the first transistor of the first type.

37. The sense amplifier of claim 36 further comprising a first charge injection cancellation circuit coupled to the second terminal of the second transistor of the second type and a second charge injection cancellation circuit coupled to the second terminal of the ninth transistor of the second type.

38. A memory cell replica sense amplifier comprising:

a replica data memory cell circuit including a replica data memory cell having similar electrical characteristics as a data memory cell, and generating a data cell voltage signal in response to current flow from said data memory cell;

a replica reference memory cell circuit including a replica reference memory cell having similar electrical characteristics as a reference memory cell, and generating a reference cell voltage signal in response to current flow from said reference memory cell; and

a differential amplifier having first and second inputs coupled to the replica data memory cell circuit and the replica reference memory cell circuit, respectively, and having an output for providing a comparison signal indicative of the difference between signals applied to the first and second inputs.

39. The memory cell replica sense amplifier of claim 38 wherein the reference memory cell is a multilevel memory cell.

40. The memory cell replica sense amplifier of claim 38 wherein the data memory cell and the reference memory cell are nonvolatile memory cells.

41. A memory cell replica sense amplifier comprising:

a differential amplifier having first and second inputs, and having an output for providing a comparison signal indicative of the difference between signals applied to the first and second inputs;

a data memory cell circuit including a memory cell;

a replica data memory cell circuit including a replica memory cell and having an output providing an output signal indicative of contents stored in said data memory cell of the data memory cell circuit and coupled to the first input of the differential amplifier;

a reference memory cell circuit including a reference memory cell; and

a replica reference memory cell circuit including a replica reference memory cell, and having an output to provide a reference voltage indicative of contents stored in said reference memory cell and coupled to the second input of the differential amplifier.

42. A differential current sense amplifier comprising:

first, second, third, and fourth current sources, the first current source being coupled between a power terminal and a first node, the second current source being coupled between the first node and a ground terminal, the third current source being coupled between the power terminal and a second node, the fourth current source being coupled between the second node and the ground terminal, the first node being configured to couple to a data current source, the second node being configured to couple to a reference current source;

a first transistor of the first type including a first terminal coupled to the first node, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel in response to a bias voltage;

a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal;

a second transistor of the first type including a first terminal coupled to the second node, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a first output node, and including a gate for controlling current in said channel and coupled to the bias voltage; and

a second transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the second type.

43. The differential current sense amplifier of claim 42 further comprising:

a third transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to said second terminal;

a third transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the second type;

a fourth transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a second output terminal, and including a gate for controlling current in said channel and coupled to the second terminal of the third transistor of the first type; and

a fourth transistor of the second type including a first terminal coupled to the second terminal of the fourth transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal and including a gate for controlling current in said channel and coupled to the first terminal of the second transistor of the second type.

44. A differential current sense amplifier comprising:

first, second, third, and fourth current sources, the first current source being coupled between a power terminal and a first node, the second current source being coupled between the. first node and a ground terminal, the third current source being coupled between the power terminal and a second node, the fourth current source being coupled between the second node and the ground terminal, the first node being configured to couple to a data current source, the second node being configured to couple to a reference current source;

a first transistor of the first type including a first terminal coupled to the first node, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel in response to a bias voltage;

a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal;

a second transistor of the first type including a first terminal coupled to the second node, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a first output node, and including a gate for controlling current in said channel and coupled to the bias voltage; and

a second transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the first terminal of the second transistor of the second type;

a third transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to said second terminal;

a third transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the second type;

a fourth transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a second output terminal, and including a gate for controlling current in said channel and coupled to the second terminal of the third transistor of the first type; and

a fourth transistor of the second type including a first terminal coupled to the second terminal of the fourth transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the ground terminal and including a gate for controlling current in said channel and coupled to the first terminal of the second transistor of the second type.

45. A differential current sense amplifier for a memory comprising:

a comparison circuit comparing a reference current and a data current and providing an output current indicative of the comparison.

46. The differential current sense amplifier of claim 45 wherein the reference current and the data current are from multilevel reference memory cells and data memory cells, respectively.

47. The differential current sense amplifier of claim 46 wherein the multilevel reference memory cells and the data memory cells are nonvolatile memory cells.

48. The differential current sense amplifier of claim 45 wherein the reference current and data current are from nonvolatile reference memory cells and nonvolatile data memory cells, respectively.

49. A differential current sense amplifier for a memory comprising:

a reference current source providing a reference current;

a data current source providing a data current and coupled to the reference current source; and

an output current source coupled to the reference current source and the output current source to provide an output current indicative of the difference between the reference current and the data current.

50. The differential current sense amplifier of claim 49 wherein the reference current source is a multilevel reference memory cell and the data current source is a multilevel data memory cell.

51. The differential current sense amplifier of claim 50 wherein the multilevel memory cells are nonvolatile memory cells.

52. The differential current sense amplifier of claim 49 wherein the reference current source is a nonvolatile reference memory cell and the data current source is a nonvolatile data memory cell.

53. A current difference sense amplifier for a memory comprising:

a reference current source providing a reference current;

a data current source providing a data current and coupled to the reference current source; and

an output stage coupled to a common node formed between the reference current source and the data current source and having an output node to provide an output current indicative of a difference between the data current and the reference current.

54. The current difference sense amplifier of claim 53 wherein the reference current source is a multilevel reference memory cell and the data current source is a multilevel data memory cell.

55. The current difference sense amplifier of claim 54 wherein the memory cells are nonvolatile memory cells.

56. The current difference sense amplifier of claim 53 wherein the reference current source is a nonvolatile reference memory cell and the data current source is a nonvolatile data memory cell.

57. The current difference sense amplifier of claim 53 wherein the output stage comprises:

a first transistor of a first type including a first terminal coupled to said common node, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to a bias voltage;

a first transistor of a second type including a first terminal coupled to the second terminal of said first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground node, and including a gate for controlling current in said channel and coupled to said second terminal; and

a second transistor of the second type including a first terminal coupled to said output node, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to said ground node, and including a gate for controlling current in said channel and coupled to said second terminal of said first transistor of the first type.