Receiver, in particular for mobile radio

• US 20030104798A1
• Filed: 01/06/2003
• Published: 06/05/2003
• Est. Priority Date: 07/05/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Boos, Zdravko
• Granted Patent: US 7,103,343 B2
• Time in Patent Office: Days
• US Class Current: 455/317
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

A receiver, in particular for mobile radio, includes a receiver branch with a mixer, downstream of an analog/digital converter. A reference generator generates a reference clock, which is fed to the converters or PLL synthesizers of the mixer by integral multiplication or division. As a result, a particularly energy-saving and space-saving circuit configuration is realized, which has a low level of mutual interference between the signals and is suitable (in particular for Universal Mobile Telecommunication System, UMTS). In a preferred embodiment, the receiver is developed into a transceiver by providing a transmission path.

Claims

1. A receiver, comprising:

a mixer having an input for receiving a reception signal and an output for tapping an intermediate frequency signal;

a phase locked loop for receiving a first reference clock and connected to said mixer;

an analog/digital converter connected to said output of said mixer for receiving a converter clock; and

a reference generator for generating a second reference clock, the second reference clock being an integral multiple of the first reference clock, and the converter clock being an integral multiple of the second reference clock.

2. The receiver according to claim 1, wherein:

said mixer is a first mixer;

a second mixer has an input for receiving another intermediate frequency signal and an output for tapping a transmission signal;

said phase locked loop is a first phase locked loop;

a second phase locked loop is provided for receiving another reference clock and is connected to said second mixer; and

a digital/analog converter is connected to said input of said second mixer for receiving another converter clock, the second reference clock is an integral multiple of the other reference clock, and the other converter clock is an integral multiple of the second reference clock.

3. The receiver according to claim 2, wherein:

the first reference clock is equal to the other reference clock; and

the converter clock is equal to the other converter clock.

4. The receiver according to claim 2, further comprising:

a first digital mixer connected downstream of said analog/digital converter;

a first interpolator connected downstream of said first digital mixer;

a second digital mixer connected upstream of said digital/analog converter; and

a second interpolator connected upstream of said second digital mixer.

5. The receiver according to claim 2, wherein:

said analog/digital converter has a first digital filter; and

said digital/analog converter includes a second digital filter.

6. The receiver according to claim 4, wherein each of said first and second interpolators has a plurality of subinterpolators configured in series.

7. The receiver according to claim 2, wherein the second reference clock has a clock frequency of substantially 13 MHz.

8. The receiver according to claim 2, wherein the second reference clock has a clock frequency of substantially 40 MHz.

9. The receiver according to claim 2, wherein the converter clocks are substantially equal to the second reference clock.

10. A receiver for mobile radio, comprising:

a mixer having an input for receiving a reception signal and an output for tapping an intermediate frequency signal;

a phase locked loop for receiving a first reference clock and connected to said mixer;

an analog/digital converter connected to said output of said mixer for receiving a converter clock; and

a reference generator for generating a second reference clock, the second reference clock being an integral multiple of the first reference clock, and the converter clock being an integral multiple of the second reference clock.