Methods and apparatus for distributing interrupts

• US 20030105798A1
• Filed: 12/03/2001
• Published: 06/05/2003
• Est. Priority Date: 12/03/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Kim, Ted, Gentry, Denton E. Jr.
• Granted Patent: US 7,328,294 B2
• Time in Patent Office: Days
• US Class Current: 718/105
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics are identified. In one example, interrupt characteristics can be compared with characteristics of other interrupts handled by processors in the multiprocessor system. Interrupt characteristics are used to select a processor to run a routine for handling the associated interrupt. Intelligent selection provides efficient and effective distribution of interrupts.

Claims

1. A method for distributing interrupt load to processors in a multiprocessor system, the method comprising:

identifying a first characteristic associated with a first interrupt;

identifying a second characteristic associated with a second interrupt;

selecting a first processor for running a first interrupt handler associated with the first interrupt, wherein the first processor is selected by comparing the first characteristic with the second characteristic, the selection of the first processor allowing distribution of interrupt load.

2. The method of claim 1, wherein the second characteristic is maintained by an interrupt controller.

3. The method of claim 1, wherein the second characteristic is maintained by a communication adapter.

4. The method of claim 1, wherein the first characteristic is a protocol of the message triggering the first interrupt.

5. The method of claim 1, wherein the first characteristic is a session of the message triggering the first interrupt.

6. The method of claim 1, wherein the first characteristic is a priority of the first interrupt.

7. The method of claim 1, wherein the first characteristic is the scheduling group of the first interrupt.

8. The method of claim 1, wherein comparing the first characteristic with the second characteristic comprises determining whether the characteristics are different.

9. The method of claim 1, wherein the first processor is configured to run an interrupt handler in parallel with a second processor.

10. An apparatus for distributing interrupt load to processors in a multiprocessor system, the apparatus comprising:

means for identifying a first characteristic associated with a first interrupt;

means for identifying a second characteristic associated with a second interrupt;

means for selecting a first processor for running a first interrupt handler associated with the first interrupt, wherein the first processor is selected by comparing the first characteristic with the second characteristic, the selection of the first processor allowing distribution of interrupt load.

11. The apparatus of claim 10, wherein the first characteristic is the scheduling group of the first interrupt.

12. The apparatus of claim 10, wherein the first characteristic comprises the scheduling group and the priority of the first interrupt.

13. The apparatus of claim 10, wherein the first processor is configured to run an interrupt handler in parallel with a second processor.

14. The apparatus of claim 10, wherein comparing the first characteristic with the second characteristic comprises determining whether the characteristics are different.

15. The apparatus of claim 10, wherein the apparatus is an interrupt controller.

16. An interrupt controller for distributing interrupt load to processors in a multiprocessor system, the apparatus comprising:

an interrupt request register coupled to a plurality of interrupt sources;

a priority resolver coupled to the interrupt request register, the priority resolver configured to receive interrupts from the interrupt request register and prioritize the interrupts;

an interrupt distributor coupled to the priority resolver, the interrupt distributor configured to select a first processor for running a first interrupt handler associated with a first interrupt, wherein the first processor is selected by comparing the first characteristic with a second characteristic associated with a second interrupt.

17. The apparatus of claim 16, wherein the first characteristic is the scheduling group of the first interrupt.

18. The apparatus of claim 16, wherein the first characteristic comprises the scheduling group and the priority of the first interrupt.

19. The apparatus of claim 16, wherein the first processor is configured to run an interrupt handler in parallel with a second processor.

20. The apparatus of claim 16, wherein comparing the first characteristic with the second characteristic comprises determining whether the characteristics are different.

21. A method for dynamic selection of a processor in a multiprocessor system, the method comprising:

identifying a first interrupt;

identifying a routine for handling the first interrupt;

dispatching the first interrupt to the first processor upon checking a recent invocation indicator associated with the first processor to allow dynamic selection of the first processor for handling the first interrupt in a multiprocessor system.

22. The method of claim 21, further comprising:

identifying a second hardware interrupt;

dispatching the second interrupt to the first processor where a first interrupt characteristic and a second interrupt characteristic are different.

23. The method of claim 22, wherein the second interrupt is dispatched to the first processor if the first and second interrupts correspond to messages of different protocols.

24. The method of claim 22, wherein the second interrupt is dispatched to the first processor if the first and second interrupts are associated with different sessions.

25. The method of claim 22, wherein the second interrupt is dispatched to the first processor if the first and second interrupts have different priorities.

26. The method of claim 22, wherein the second interrupt is dispatched to the first processor if the first and second interrupts are associated with different scheduling group.

27. The method of claim 22, wherein the first processor is configured to running the routine for handling the interrupt in parallel with a second processor.

28. An apparatus for dynamic selection of a processor in a multiprocessor system, the apparatus comprising:

means for identifying a first interrupt;

means for identifying a routine for handling the first interrupt;

means for dispatching the first interrupt to the first processor upon checking a recent invocation indicator associated with the first processor to allow dynamic selection of the first processor for handling the first interrupt in a multiprocessor system.

29. The apparatus of claim 28, further comprising:

means for identifying a second hardware interrupt;

means for dispatching the second interrupt to the first processor where a first interrupt characteristic and a second interrupt characteristic are different.

30. The apparatus of claim 29, wherein the second interrupt is dispatched to the first processor if the first and second interrupts correspond to messages of different protocols.

31. The apparatus of claim 29, wherein the second interrupt is dispatched to the first processor if the first and second interrupts are associated with different sessions.

32. The apparatus of claim 29, wherein the second interrupt is dispatched to the first processor if the first and second interrupts have different priorities.

33. The apparatus of claim 29, wherein the second interrupt is dispatched to the first processor if the first and second interrupts are associated with different scheduling group.

34. The apparatus of claim 29, wherein the first processor is configured to run the routine for handling the interrupt in parallel with a second processor.

35. The apparatus of claim 28, wherein the apparatus is an interrupt controller.