Emulation of memory clock enable pin and use of chip select for memory power control

• US 20030105932A1
• Filed: 11/30/2001
• Published: 06/05/2003
• Est. Priority Date: 11/30/2001
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Close, Paul G., David, Howard S.
• Application Number:
  US10/010,030
• Publication Number:
  US 20030105932A1
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for powering down a memory device by deasserting a chip select line for a predetermined number of consecutive clock cycles and for powering up the memory device by asserting the chip select line.

Claims

1. A method comprising:

setting a predetermined number of consecutive clock cycles to occur on a clock signal line;

deasserting a chip select for the predetermined number of consecutive clock cycles;

powering down a memory device in response to the deasserting of the chip select line for the predetermined number of clock cycles;

asserting the chip select line; and

powering up the memory device in response to the asserting of the chip select line.

2. The method of claim 1, wherein the setting of a predetermined number of consecutive clock cycles comprises setting at least one bit in at least one register of the memory device.

3. The method of claim 2, wherein the at least one bit in at least one register of the memory device is a bit used in setting at least one timing parameter of the memory device.

4. The method of claim 1, wherein the asserting and the deasserting of the chip select line occur in synchronization with a phase of clock cycles occurring on the clock signal line.

5. The method of claim 1, further comprising ceasing activity on at least one command line prior to deasserting the chip select line, and restoring activity on the at least one command line after asserting the chip select line.

6. The method of claim 1, further comprising preventing the memory device from powering down by asserting the chip select line before the predetermined number of consecutive clock cycles occurs since the chip select line was last asserted.

7. A memory controller comprising:

circuitry to carry out operations with a memory device; and

an interface that couples the circuitry to a memory device, the interface being comprised of a clock signal line and a chip select line, the chip select line being used by the memory controller to power down the memory device by deasserting the chip select line for a predetermined number of consecutive clock cycles occurring on the clock signal line, and to power up the memory device by asserting the chip select line.

8. The memory controller of claim 7, wherein the chip select line is further used by the memory controller to prevent the memory device from powering down by asserting the chip select line before the predetermined number of consecutive clock cycles has occurred since the chip select line was last asserted.

9. The memory controller of claim 7, wherein the memory controller asserts and deasserts the chip select line in synchronization with a phase of clock cycles occurring on the clock signal line.

10. The memory controller of claim 7, wherein the memory controller further ceases activity on at least one command line of the memory interface prior to deasserting the chip select line, and restores activity on the at least one command line after asserting the chip select line.

11. The memory controller of claim 7, wherein the memory controller sets the predetermined number of consecutive clock cycles by programming at least one bit in a register in the memory device.

12. The memory controller of claim 7, wherein the clock signal line is comprised of a pair of signal lines of opposing polarity transmitting a differential clock signal.

13. A memory device comprising:

a plurality of storage locations;

an interface to a memory controller comprised of a clock signal line and a chip select line, where the memory device powers down if the chip select line is deasserted for a predetermined number of consecutive clock cycles occurring on the clock signal line, and where the memory device powers up if the chip select line is asserted.

14. The memory device of claim 13, wherein the memory device can be prevented from powering down by asserting the chip select line before the predetermined number of consecutive clock cycles has occurred since the chip select line was last asserted.

15. The memory device of claim 13, wherein the memory device samples the chip select line in synchronization with a phase of clock cycles occurring on the clock signal line to determine if the chip select line is being asserted.

16. The memory device of claim 13, further comprising at least one bit in at least one register that allows the predetermined number of consecutive clock cycles to be programmed.

17. A computer system comprising:

a processor;

a memory device;

an interface serving to couple the processor to the memory device, the interface being comprised of a clock signal line and a chip select line, the chip select line being used to power down the memory device by deasserting the chip select line for a predetermined number of consecutive clock cycles occurring on the clock signal line, and to power up the memory device by asserting the chip select line.

18. The computer system of claim 17, wherein the chip select line is further used to prevent the memory device from powering down by asserting the chip select line before the predetermined number of consecutive clock cycles has occurred since the chip select line was last asserted.

19. The computer system of claim 17, wherein the chip select line is asserted and deasserted in synchronization with a phase of clock cycles occurring on the clock signal line.

20. The computer system of claim 17, wherein activity ceases on at least one command line of the memory interface prior to deasserting the chip select line, and activity is restored on the at least one command line after asserting the chip select line.

21. The computer system of claim 17, wherein the predetermined number of consecutive clock cycles is set by programming at least one bit in a register in the memory device.

22. The computer system of claim 21, wherein the at least one bit in a register of the memory device is a bit used in setting at least one timing parameter of the memory device.

23. The computer system of claim 17, wherein the clock signal line is comprised of a pair of signal lines of opposing polarity transmitting a differential clock signal.

24. The computer system of claim 17, wherein the memory device comprises an input that allows the memory device to be powered down and powered up that is tied off.

25. A computer-readable medium containing a sequence of instructions, which when executed by a processor causes the processor to power down a memory device by deasserting a chip select line of a memory interface that serves to couple the processor to the memory device for a predetermined number of consecutive clock cycles occurring on a clock signal line of the memory interface, and to power up the memory device by asserting the chip select line.

26. The computer-readable medium of claim 25, wherein the chip select line is further used to prevent the memory device from powering down by asserting the chip select line before the predetermined number of consecutive clock cycles occurs since the chip select line was last asserted.

27. The computer-readable medium of claim 25, wherein the chip select line is asserted and deasserted in synchronization with a phase of clock cycles occurring on the clock signal line.

28. The computer-readable medium of claim 25, wherein activity is ceased on at least one command line of the memory interface prior to deasserting the chip select line, and activity is restored to the at least one command line after the chip select line is asserted.

29. The computer-readable medium of claim 25, wherein the predetermined number of consecutive clock cycles is set by programming at least one bit in a register in the memory device.