Trench MOSFET device with polycrystalline silicon source contact structure
First Claim
1. A trench MOSFET transistor device comprising:
- a silicon substrate of a first conductivity type;
a silicon epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;
a trench extending into said epitaxial layer from an upper surface of said epitaxial layer;
an insulating layer lining at least a portion of said trench;
a conductive region within said trench adjacent said insulating layer;
a body region of a second conductivity type provided within an upper portion of said epitaxial layer and adjacent said trench;
a source region of said first conductivity type provided within an upper portion of said body region and adjacent said trench;
an upper region of second conductivity type within an upper portion of said body region and adjacent said source region, said upper region having a higher majority carrier concentration than said body region; and
a source contact region disposed on said epitaxial layer upper surface, said source contact region comprising;
(a) a doped polycrystalline silicon contact region in electrical contact with said source region and (b) a metal contact region adjacent said doped polycrystalline silicon contact region and in electrical contact with said source region and with said upper region.
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Accused Products
Abstract
A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.
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Citations
21 Claims
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1. A trench MOSFET transistor device comprising:
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a silicon substrate of a first conductivity type;
a silicon epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;
a trench extending into said epitaxial layer from an upper surface of said epitaxial layer;
an insulating layer lining at least a portion of said trench;
a conductive region within said trench adjacent said insulating layer;
a body region of a second conductivity type provided within an upper portion of said epitaxial layer and adjacent said trench;
a source region of said first conductivity type provided within an upper portion of said body region and adjacent said trench;
an upper region of second conductivity type within an upper portion of said body region and adjacent said source region, said upper region having a higher majority carrier concentration than said body region; and
a source contact region disposed on said epitaxial layer upper surface, said source contact region comprising;
(a) a doped polycrystalline silicon contact region in electrical contact with said source region and (b) a metal contact region adjacent said doped polycrystalline silicon contact region and in electrical contact with said source region and with said upper region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A trench MOSFET transistor device comprising:
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an N-type silicon substrate;
an N-type silicon epitaxial layer over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;
a trench extending into said epitaxial layer from an upper surface of said epitaxial layer;
a silicon oxide insulating layer lining at least a portion of said trench;
a doped polycrystalline silicon conductive region within said trench adjacent said insulating layer;
a P-type body region provided within an upper portion of said epitaxial layer and adjacent said trench;
an N-type source region provided within an upper portion of said body region and adjacent said trench;
a P-type upper region within an upper portion of said body region and adjacent said source region, said upper region having a higher majority carrier concentration than said body region;
a borophosphosilicate glass insulating region disposed over said conductive region, said insulating region extending above said epitaxial layer upper surface; and
a source contact region disposed on said epitaxial layer upper surface and laterally adjacent said insulating region, said source contact region comprising;
(a) a doped polycrystalline silicon contact region having N-type doping and (b) a metal contact region adjacent said doped polycrystalline silicon contact region and in electrical contact with said source region and with said upper region.
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17. A method of forming a trench MOSFET transistor device comprising:
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providing a silicon substrate of a first conductivity type;
depositing a silicon epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;
etching a trench extending into said epitaxial layer from an upper surface of said epitaxial layer;
forming an insulating layer that lines at least a portion of said trench;
forming a conductive region within said trench and adjacent said insulating layer;
forming a body region of a second conductivity type within an upper portion of said epitaxial layer and adjacent said trench;
forming a source region of said first conductivity type within an upper portion of said body region and adjacent said trench;
forming an upper region of second conductivity type within an upper portion of said body region and adjacent said source region, said upper region having a higher majority carrier concentration than said body region; and
forming a source contact region on said epitaxial layer upper surface, said source contact region comprising (a) a doped polycrystalline silicon contact region in electrical contact with said source region and (b) a metal contact region adjacent said doped polycrystalline silicon contact region and in electrical contact with said source region and with said upper region. - View Dependent Claims (18, 19, 20, 21)
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Specification