Ultra-rugged biometric I.C. sensor and method of making the same

• US 20030107097A1
• Filed: 07/01/2002
• Published: 06/12/2003
• Est. Priority Date: 07/14/1999
• Status: Abandoned Application

• Current Assignee: Douglas C. Mcarthur, John E. Meyer, Thomas L. Andrade
• Original Assignee: Douglas C. Mcarthur, John E. Meyer, Thomas L. Andrade
• Inventors: Meyer, John E., McArthur, Douglas C., Andrade, Thomas l.
• Application Number:
  US10/191,394
• Publication Number:
  US 20030107097A1
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: G06V 40/1329 Protecting the fingerprint sensor against damage caused by the finger

Abstract

An ultra-rugged biometric integrated circuit sensor and method for constructing the same is provided. The sensor comprises a sensing area and a control electronics area, and, as result of its construction, the sensor has a topology whereby the sensing area is elevated with respect to the control electronics area. In other words, a depression is created on the sensor surface that allows the control electronics to escape damaging impacts by external forces. According to one embodiment, the sensing area and control electronics area are structures such there is no overlap between either area, except where the sensing area is electrically coupled to the control electronics. According to another embodiment, the sensor further comprises a electric static discharge structure that creates a least resistant path to ground. The electric static discharge structure further protects the control electronics from high voltage surges encountered in normal operation.

Claims

1. A semiconductor device for biometric identification, comprising:

a rigid sensing area;

a control electronics area; and

at least one dielectric layer disposed in both said control electronics area and said sensing area, the dielectric layer including an etched region above said control electronics area, the etched region creating a higher topology in said sensing area than in said control electronics area.

2. The device of claim 1, further comprising:

a capacitor plate located in said sensing area; and

a circuit device located in said control electronics area;

wherein said sensing area and said control electronics area do not cross over, except where said capacitor plate is electrically coupled to said circuit device.

3. The device of claim 1, wherein said semiconductor device comprises:

a substrate;

an electrically insulating layer having a contact, said electrically insulating layer being formed over said substrate;

a first conductive line formed over said electrically insulating layer and said contact;

a first dielectric layer having a first via, said first dielectric layer being formed over said first conductive line and said electrically insulating layer;

a second conductive line formed over said first dielectric layer and into said first via;

a second dielectric layer having a second via, said second dielectric layer being formed over said first dielectric layer and said first conductive line;

a third conductive line formed over said second dielectric layer and said second conductive line; and

a passivation layer over said third conductive line and said second dielectric layer.

4. The device of claim 1, wherein said sensing area comprises said third conductive line.

5. The device of claim 1, wherein said control electronics area comprises said contact, said first conductive line, and said second conductive line.

6. The device of claim 3, further comprising:

a fourth dielectric layer, beneath the second dielectric layer; and

wherein said second dielectric layer comprises;

a third dielectric layer, disposed over said fourth dielectric layer; and

a spin-on-glass coating disposed over said fourth dielectric layer.

7. The device of claim 3. wherein said passivation layer comprises a low stress compressive material.

8. The device of claim 3, further comprising a plate between said substrate and said third conductive line.

9. The device of claim 1, wherein said semiconductor device comprises a plurality of said rigid sensing elements.

10. The device of claim 9, further comprising an electric static discharge (ESD) structure between at least two of said rigid sensing elements.

11. A semiconductor device for biometric identification, comprising:

a rigid sensing area;

a control electronics area;

at least one dielectric layer disposed in both said control electronics area and said rigid sensing area, the dielectric layer including an etched region above said control electronics area; and

a passivation layer, disposed over said dielectric layer, wherein the etched region creates a higher topology in said rigid sensing area than in said control electronics area with respect to said passivation layer.

12. The device of claim 11, wherein said semiconductor device further comprises:

a substrate, supporting said rigid sensing area and said control electronics area; and

13. The device of claim 12, wherein said semiconductor device further comprises:

a first conductive line disposed over said electrically insulating layer; and

a contact coupled with said first conductive line and said substrate.

14. The device of claim 13, wherein said semiconductor device further comprises:

a first dielectric layer disposed over said first conductive line and said electrically insulating layer; and

a second conductive line disposed over said first dielectric layer.

15. The device of claim 14, wherein said semiconductor device further-comprises a first via coupled with said first dielectric layer and said first conductive line.

16. The device of claim 15, wherein said semiconductor device further comprises a second dielectric layer disposed over said first dielectric layer and said second conductive line.

17. A semiconductor device for biometric identification, comprising:

a rigid sensing area, said rigid sensing area including a capacitor plate;

a control electronics area, said control electronics area including a circuit device; and

at least one dielectric layer disposed in both said control electronics area and said sensing area, the dielectric layer including an etched region above said circuit device;

wherein said rigid sensing area and said control electronics area do not cross over, except where said capacitor plate is electrically coupled to said circuit device.

18. The device of claim 17, wherein said semiconductor device further comprises:

a substrate; and

an electrically insulating layer disposed over said substrate.

19. The device of claim 18, wherein said semiconductor device further comprises:

a first conductive line disposed over said electrically insulating layer; and

a contact coupled with said first conductive line and said substrate.

20. The device of claim 19, wherein said semiconductor device further comprises:

a first dielectric layer disposed over said first conductive line and said electrically insulating layer; and

a second conductive line disposed over said first dielectric layer.

21. The device of claim 20, wherein said semiconductor device further comprises a first via coupled with said first dielectric layer and said first conductive line.

22. The device of claim 21, wherein said semiconductor device further comprises a second dielectric layer disposed over said first dielectric layer and said second conductive line.

23. The semiconductor device of claim 17, further comprising a passivation layer disposed over said capacitor plate and said circuit device, said passivation layer configured to receive a finger at a first surface of said semiconductor device, the first surface above said capacitor plate, and further configured to avoid the finger at a second surface of said semiconductor device, said second surface above the circuit device.