Multi-chip package (MCP) with a conductive bar and method for manufacturing the same
First Claim
1. A multi-chip package (MCP), comprising:
- a plurality of stacked semiconductor chips, each chip including;
a chip pad on a main surface thereof;
a first insulating layer overlying the chip pad, the first insulating layer having an opening to expose a portion of the chip pad;
a pad redistribution line formed on the first insulating layer;
a second insulating layer covering the pad redistribution line, wherein a via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer;
a protective layer formed on the bottom of the lowest semiconductor chip, the protective layer including a conductive pad formed opposite the bottom of the lowest semiconductor chip;
a conductive bar extending through the via holes of the stacked semiconductor chips, from the conductive pad, and being electrically connected to the pad redistribution line of the stacked semiconductor chips.
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Accused Products
Abstract
A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.
69 Citations
30 Claims
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1. A multi-chip package (MCP), comprising:
a plurality of stacked semiconductor chips, each chip including;
a chip pad on a main surface thereof;
a first insulating layer overlying the chip pad, the first insulating layer having an opening to expose a portion of the chip pad;
a pad redistribution line formed on the first insulating layer;
a second insulating layer covering the pad redistribution line, wherein a via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer;
a protective layer formed on the bottom of the lowest semiconductor chip, the protective layer including a conductive pad formed opposite the bottom of the lowest semiconductor chip;
a conductive bar extending through the via holes of the stacked semiconductor chips, from the conductive pad, and being electrically connected to the pad redistribution line of the stacked semiconductor chips. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor chip for manufacturing a MCP, the chip comprising:
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a chip pad on a main surface thereof;
a passivation layer formed overlying the chip pad, the passivation layer having a first opening to expose a portion of the chip pad;
a first insulating layer overlying the passivation layer, the first insulating layer having a second opening to expose the portion of the chip pad;
a pad redistribution line formed on the first insulating layer; and
a second insulating layer covering the pad redistribution line, wherein a via hole is formed through the chip, the first insulating layer, a pad redistribution pattern and the second insulating layer.
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10. A method for manufacturing a MCP, the method comprising:
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forming a first insulating layer on the semiconductor chip having a chip pad, the first insulating layer having an opening to expose a portion of the chip pad;
forming a pad redistribution line on the first insulating layer, the pad redistribution line electrically connected to the chip pad;
forming a second insulating layer on the first insulating layer to cover the pad redistribution line;
forming a via hole extending through the chip, the first insulating layer, a pad redistribution pattern and the second insulating layer. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method for forming a substrate for manufacturing an MCP having a plurality of stacked semiconductor chips, the method comprising:
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forming a polymer layer on one side of a substrate;
forming a conductive pad overlying the polymer layer;
forming a protective layer overlying the conductive pad;
forming a first opening in the protective layer to expose a portion of the conductive pad; and
forming a conductive bar extending upwardly from the conductive pad. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A method for forming a MCP, wherein the MCP comprises a plurality of stacked semiconductor chips, each chip including a chip pad on a main surface thereof;
- a first insulating layer overlying the chip pad, the first insulating layer having an opening to expose a portion of the chip pad;
a pad redistribution line formed on the first insulating layer, a second insulating layer covering the pad redistribution line, wherein a via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer, the method comprising;
forming a polymer layer on one side of a substrate;
forming a conductive pad overlying the polymer layer;
forming a protective layer overlying the conductive pad;
forming an opening in the protective layer to expose a portion of the conductive pad; and
forming a conductive bar extending upwardly from the conductive pad;
inserting the conductive bar into the via holes and stacking the plurality of the semiconductor chips on the substrate such that the conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad;
electrically connecting the conductive bar to the pad redistribution line. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
- a first insulating layer overlying the chip pad, the first insulating layer having an opening to expose a portion of the chip pad;
Specification