Inrush current suppression circuit

• US 20030107859A1
• Filed: 03/14/2002
• Published: 06/12/2003
• Est. Priority Date: 12/06/2001
• Status: Active Grant

• Current Assignee: Delta Electronics Incorporated
• Original Assignee: Delta Electronics Incorporated
• Inventors: Hsu, Chih-Ming, Pan, Kuang-Hua
• Granted Patent: US 6,646,842 B2
• Time in Patent Office: Days
• US Class Current: 361/58
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16

Abstract

An inrush current suppression circuit is installed between a DC voltage and a load with a parallel system capacitor. The inrush current suppression circuit includes a first current limiting circuit which includes a first resistor, a first controlled switch, and a second controlled switch. The inrush current suppression circuit further includes a second current limiting circuit which further includes a second resistor, a third controlled switch, and an energy-storing capacitor. The second current limiting circuit is electrically connected in parallel to the system capacitor, and the first current limiting circuit is electrically connected with the DC voltage and the second current limiting circuit. When the DC voltage is detected, the first controlled switch is conducted. When a voltage of two ends of the load reaches a first threshold value, the second controlled switch is conducted so as to bypass the first resistor. When a voltage of the energy-storing capacitor reaches a second threshold value, the third controlled switch is conducted so as to bypass the second resistor.

Claims

1. An inrush current suppression circuit installed between a DC voltage and a load with a parallel system capacitor comprising:

a first current limiting circuit comprising;

a first resistor;

a first controlled switch; and

a second controlled switch wherein said first controlled switch and said first resistor are electrically connected in series, and said second controlled switch is electrically connected in parallel to said first controlled switch and said first resistor; and

a second current limiting circuit comprising;

a second resistor;

a third controlled switch; and

an energy-storing capacitor wherein said second resistor and said energy-storing capacitor are electrically connected in series, said second resistor is electrically connected in parallel to said third controlled switch, said second current limiting circuit is electrically connected in parallel to said system capacitor, and said first current limiting circuit is electrically connected with said DC voltage and said second current limiting circuit,

whereby, when said DC voltage is detected, the first controlled switch is conducted;

when a voltage of two ends of said load reaches a first threshold value, said second controlled switch is conducted so as to bypass said first resistor; and

when a voltage of said energy-storing capacitor reaches a second threshold value, said third controlled switch is conducted so as to bypass said second resistor.

2. The inrush current suppression circuit as claimed in claim 1, wherein said load is a DC-DC converter.

3. The inrush current suppression circuit as claimed in claim 1, wherein said first controlled switch is selected from a group consisting of a relay, a bipolar transistor, and a MOSFET (metal-oxide-semiconductor field-effect transistor).

4. The inrush current suppression circuit as claimed in claim 1, wherein said second controlled switch is a MOSFET.

5. The inrush current suppression circuit as claimed in claim 1, wherein said third controlled switch is a MOSFET.

6. The inrush current suppression circuit as claimed in claim 1, wherein said first threshold value is from 30% to 80% of the DC voltage.

7. The inrush current suppression circuit as claimed in claim 6, wherein said first threshold value is from 50% to 70% of the DC voltage.

8. The inrush current suppression circuit as claimed in claim 1, wherein said second threshold value is from 70% to 100% of the DC voltage.

9. The inrush current suppression circuit as claimed in claim 8, wherein said second threshold value is from 80% to 100% of the DC voltage.

10. The inrush current suppression circuit as claimed in claim 1, wherein said second controlled switch is soft turned-on.

11. The inrush current suppression circuit as claimed in claim 1, wherein said third controlled switch is soft turned-on.

12. An inrush current suppression circuit installed between a DC voltage and a load with a parallel system capacitor comprising:

a first current limiting circuit comprising;

a first resistor;

a first controlled switch; and

a second controlled switch wherein said first controlled switch and said first resistor are electrically connected in series, and said second controlled switch is electrically connected in parallel to said first controlled switch and said first resistor; and

a second current limiting circuit comprising;

a second resistor;

a third controlled switch; and

an energy-storing capacitor wherein said second resistor and said energy-storing capacitor are electrically connected in series, said second resistor is electrically connected in parallel to said third controlled switch, said second current limiting circuit is electrically connected in parallel to said system capacitor, and said first current limiting circuit is electrically connected with said DC voltage and said second current limiting circuit,

whereby, when said DC voltage is detected, the first controlled switch is conducted;

when a voltage of two ends of said load reaches a first threshold value, said second controlled switch is soft turned-on so as to bypass said first resistor; and

when a voltage of said energy-storing capacitor reaches a second threshold value, said third controlled switch is soft turned-on so as to bypass said second resistor.