Inrush current suppression circuit
First Claim
1. An inrush current suppression circuit installed between a DC voltage and a load with a parallel system capacitor comprising:
- a first current limiting circuit comprising;
a first resistor;
a first controlled switch; and
a second controlled switch wherein said first controlled switch and said first resistor are electrically connected in series, and said second controlled switch is electrically connected in parallel to said first controlled switch and said first resistor; and
a second current limiting circuit comprising;
a second resistor;
a third controlled switch; and
an energy-storing capacitor wherein said second resistor and said energy-storing capacitor are electrically connected in series, said second resistor is electrically connected in parallel to said third controlled switch, said second current limiting circuit is electrically connected in parallel to said system capacitor, and said first current limiting circuit is electrically connected with said DC voltage and said second current limiting circuit, whereby, when said DC voltage is detected, the first controlled switch is conducted;
when a voltage of two ends of said load reaches a first threshold value, said second controlled switch is conducted so as to bypass said first resistor; and
when a voltage of said energy-storing capacitor reaches a second threshold value, said third controlled switch is conducted so as to bypass said second resistor.
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Accused Products
Abstract
An inrush current suppression circuit is installed between a DC voltage and a load with a parallel system capacitor. The inrush current suppression circuit includes a first current limiting circuit which includes a first resistor, a first controlled switch, and a second controlled switch. The inrush current suppression circuit further includes a second current limiting circuit which further includes a second resistor, a third controlled switch, and an energy-storing capacitor. The second current limiting circuit is electrically connected in parallel to the system capacitor, and the first current limiting circuit is electrically connected with the DC voltage and the second current limiting circuit. When the DC voltage is detected, the first controlled switch is conducted. When a voltage of two ends of the load reaches a first threshold value, the second controlled switch is conducted so as to bypass the first resistor. When a voltage of the energy-storing capacitor reaches a second threshold value, the third controlled switch is conducted so as to bypass the second resistor.
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Citations
12 Claims
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1. An inrush current suppression circuit installed between a DC voltage and a load with a parallel system capacitor comprising:
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a first current limiting circuit comprising;
a first resistor;
a first controlled switch; and
a second controlled switch wherein said first controlled switch and said first resistor are electrically connected in series, and said second controlled switch is electrically connected in parallel to said first controlled switch and said first resistor; and
a second current limiting circuit comprising;
a second resistor;
a third controlled switch; and
an energy-storing capacitor wherein said second resistor and said energy-storing capacitor are electrically connected in series, said second resistor is electrically connected in parallel to said third controlled switch, said second current limiting circuit is electrically connected in parallel to said system capacitor, and said first current limiting circuit is electrically connected with said DC voltage and said second current limiting circuit, whereby, when said DC voltage is detected, the first controlled switch is conducted;
when a voltage of two ends of said load reaches a first threshold value, said second controlled switch is conducted so as to bypass said first resistor; and
when a voltage of said energy-storing capacitor reaches a second threshold value, said third controlled switch is conducted so as to bypass said second resistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An inrush current suppression circuit installed between a DC voltage and a load with a parallel system capacitor comprising:
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a first current limiting circuit comprising;
a first resistor;
a first controlled switch; and
a second controlled switch wherein said first controlled switch and said first resistor are electrically connected in series, and said second controlled switch is electrically connected in parallel to said first controlled switch and said first resistor; and
a second current limiting circuit comprising;
a second resistor;
a third controlled switch; and
an energy-storing capacitor wherein said second resistor and said energy-storing capacitor are electrically connected in series, said second resistor is electrically connected in parallel to said third controlled switch, said second current limiting circuit is electrically connected in parallel to said system capacitor, and said first current limiting circuit is electrically connected with said DC voltage and said second current limiting circuit, whereby, when said DC voltage is detected, the first controlled switch is conducted;
when a voltage of two ends of said load reaches a first threshold value, said second controlled switch is soft turned-on so as to bypass said first resistor; and
when a voltage of said energy-storing capacitor reaches a second threshold value, said third controlled switch is soft turned-on so as to bypass said second resistor.
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Specification