Method for operating a semiconductor memory, and semiconductor memory
First Claim
1. A method for operating a semiconductor memory having at least three memory areas each including a plurality of memory addresses, which comprises:
- connecting the memory addresses from the at least three memory areas in parallel with one another to form a group of memory addresses having a respective memory address from each of the at least three memory areas;
writing a given information item to all of said memory addresses in said group;
reading the information items from each of said memory addresses in said group; and
performing an error check on the information items by checking if the information items read from said memory addresses in said group are identical to one another.
4 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of memory areas, preferably memory banks, and read the information items therefrom. A checking unit contains synchronization circuits compares the data values that are read and, if the information items that are read differ, can ascertain and possibly immediately correct storage errors. The method of operating the memory enables quasi-random access to memory cells using a permutation circuit. In a test mode for the semiconductor memory, an error log circuit can output error log data instead of or in addition to data values that are read.
16 Citations
29 Claims
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1. A method for operating a semiconductor memory having at least three memory areas each including a plurality of memory addresses, which comprises:
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connecting the memory addresses from the at least three memory areas in parallel with one another to form a group of memory addresses having a respective memory address from each of the at least three memory areas;
writing a given information item to all of said memory addresses in said group;
reading the information items from each of said memory addresses in said group; and
performing an error check on the information items by checking if the information items read from said memory addresses in said group are identical to one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor memory, comprising:
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at least three memory areas each having a multiplicity of memory addresses for storing information items;
synchronization circuits for connecting memory addresses from said at least three memory areas in parallel with one another to form a group and to allow each read and write operation to access said group of memory addresses and for routing a given information item to all of said memory addresses in said group during a write operation; and
a checking unit for checking if said information items at said memory addresses in said group are identical to one another. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification