Silicon semiconductor wafer, and process for producing a multiplicity of semiconductor wafers

• US 20030109139A1
• Filed: 11/14/2002
• Published: 06/12/2003
• Est. Priority Date: 12/06/2001
• Status: Active Grant

• Current Assignee: Siltronic AG (Dr. Alexander Wacker Familiengesellschaft Mit Beschrã¤Nkter Haftung)
• Original Assignee: Siltronic AG (Dr. Alexander Wacker Familiengesellschaft Mit Beschrã¤Nkter Haftung)
• Inventors: Altmann, Thomas, Huber, Anton, Heilmaier, Alexander, Wenski, Guido
• Granted Patent: US 6,861,360 B2
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: B24B 37/0056 taking regard of the pH-value of lapping agents
• CPC Class Codes: B24B 37/042 operating processes therefor
• CPC Class Codes: B24B 37/08 for double side lapping
• CPC Class Codes: B24B 49/16 taking regard of the load
• CPC Class Codes: H01L 21/02024 Mirror polishing

Abstract

A silicon semiconductor wafer with a diameter of greater than or equal to 200 mm and a polished front surface and a polished back surface and a maximum local flatness value SFQR_m-1 of less than or equal to 0.13 μm, based on a surface grid of segments with a size of 26 mm×8 mm on the front surface, wherein the maximum local height deviation P/V(10×10)_m-1 of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×10 mm. There is also a process for producing a multiplicity of silicon semiconductor wafers by simultaneous double-side polishing between in each case one lower polishing plate and one upper polishing plate, which rotate, are parallel to one another and to which polishing cloth has been adhesively bonded, while a polishing agent, which contains abrasives or colloids, is being supplied, with at least 2 μm of silicon being removed, wherein a predetermined proportion of the semiconductor wafers is at least partially polished using a lower polishing pressure, and a further proportion of the semiconductor wafers is polished using a higher polishing pressure.

Claims

1. A silicon semiconductor wafer having a diameter of greater than or equal to 200 mm comprising

a polished front surface and a polished back surface and a maximum local flatness value SFQR_m-1 of less than or equal to 0.13 μ

m, based on a surface grid of segments with a size of 26 mm×

8 mm on the front surface, wherein the maximum local height deviation P/V(10×

10)_max of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×

10 mm.

2. The semiconductor wafer as claimed in claim 1,

wherein in addition the maximum local height deviation P/V(2×

2)_max of the front surface from an ideal plane is less than or equal to 20 nm, based on sliding subregions with dimensions of 2 mm×

2 mm.

3. The semiconductor wafer as claimed in claim 1,

wherein the silicon region, which is close to the surface, of the front surface has an electrical performance which deviates from that of a remainder of the silicon wafer down to a depth of from 0.5 to 10 μ

m.

4. The semiconductor wafer as claimed in claim 3,

wherein a differing electrical performance is produced in a manner selected from the group consisting of by applying an epitaxial coating of silicon with a different dopant content and by thermal dopant depletion.

25. In a method for the fabrication of integrated semiconductor components, the improvement which comprises utilizing the silicon semiconductor wafer as claimed in claim 1 for the fabrication of integrated semiconductor components.

5. A process for producing a multiplicity of silicon semiconductor wafers comprising

simultaneous double-side polishing between in each case one lower polishing plate and one upper polishing plate, which rotate, are parallel to one another and to which polishing cloth has been adhesively bonded,

while a polishing agent, which contains a substance selected from the group consisting of abrasives and colloids, is being supplied, with at least 2 μ

m of silicon being removed,

wherein a predetermined proportion of the semiconductor wafers is at least partially polished using a lower polishing pressure, and a further proportion of the semiconductor wafers is polished rising a higher polishing pressure.

6. The process as claimed in claim 5,

wherein the semiconductor wafers, during the double-side polishing, rest in cutouts in driven carriers and in this way are moved along a geometric path.

7. The process as claimed in claim 5,

wherein a lower polishing cloth and an upper polishing cloth with a hardness of 60 to 90 (Shore A) are used and a polishing agent with an SiO₂ solids content of 1% to 10% by weight and a pH of 9.5 to 12.5 is supplied;

and

wherein the percent by weight is based upon the total weight of the polishing agent.

8. The process as C claimed in claim 5,

wherein a proportion of a multiplicity of the semiconductor wafers which is polished at least partially using a lower polishing pressure is polished using carriers whose thickness is dimensioned to be 1 to 20 μ

m less than a thickness of this proportion of fully polished semiconductor wafers.

9. The process as claimed in claim 5,

wherein a proportion of a multiplicity of the semiconductor wafers which is at least partially polished using a lower polishing pressure is polished at a polishing pressure which is such that it leads to a maximum local height deviation P/V(10×

10)_max of the front surface of the semiconductor wafer from an ideal plane in sliding subregions of 10 mm×

10 mm which is as low as possible, and

the proportion of the multiplicity of the semiconductor wafers which is polished using a higher polishing pressure is polished at a polishing pressure which is such that, without the height deviation from an ideal plane being taken into account, it leads to the highest possible installation throughput while providing semiconductor wafers which are otherwise of equivalent quality to the semiconductor wafers which have been polished using a lower polishing pressure.

10. The process as claimed in claim 9,

wherein an optimum lower polishing pressure is determined in preliminary vests and is then transferred to large-scale industrial manufacture.

11. The process as claimed in claim 9,

wherein the optimum lower polishing pressure is from 0.12 to 0.18 bar.

12. The process as claimed in claim 9,

wherein if from 5 μ

m to 50 μ

m of silicon is removed, at least half of the silicon removed is polished using the optimum lower polishing pressure.

13. The process an claimed in claim 9,

wherein each semiconductor wafer of the proportion of the multiplicity of the semiconductor wafers which has been polished using an optimum lower polishing pressure has a maximum local flatness value SFQR_m-1 of less than or equal to 0.13 μ

m, based on a surface grid of segments with a size of 26 mm×

8 mm on the front surface, and a maximum local height deviation P/V(10×

10)_max of the front surface from an ideal plane of less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×

10 mm.

14. The process as claimed in claim 13,

wherein each semiconductor wafer of the proportion of the multiplicity of the silicon semiconductor wafers which has been polished using the optimum lower polishing pressure additionally has a maximum local height deviation P/V(2×

2)_max of the front surface from all ideal plane of less than or equal to 20 nm, based on sliding subregions with dimensions of 2 mm×

2 mm.

15. A process for producing a silicon semiconductor wafer as a predetermined proportion of a multiplicity of semiconductor wafers,

each silicon semiconductor wafer having a diameter of greater than or equal to 200 mm comprising a polished front surface and a polished back surface and a maximum local flatness value SFQR_m-1 of less than or equal to 0.13 μ

m, based on a surface grid of segments with a size of 26 mm×

8 mm on the front surface, wherein the maximum local height deviation P/V(10×

10)_max of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×

10 mm;

which comprises the following process steps being carried out sequentially;

(a) using a wire saw to saw a single crystal, which substantially comprises silicon;

(b) bringing about mechanical removal of silicon from a front surface and a back surface of the semiconductor wafer; and

(c) simultaneous double-side polishing of a front surface and a back surface of the semiconductor wafer as claimed in claim 5.

16. The process as claimed in claim 15,

wherein step (b) is carried out as a lapping step.

17. The process as claimed in claim 15,

wherein step (b) is carried out in a manner selected from the group consisting of a grinding step and a combination of a plurality of grinding steps.

18. The process as claimed in claim 15,

wherein wet-chemical etching of the machined semiconductor wafer takes place between steps (b) and (c).

19. The process as claimed in claim 15,

wherein polishing of an edge of the semiconductor wafers takes place in a manner selected from the group consisting of before, during, and after the simultaneous polishing of a front surface and a back surface.

20. The process as claimed in claim 15,

wherein step (c) is carried out at a polishing pressure which is optimum for minimizing the height deviation of the front surface from an ideal plane.

21. The process as claimed in claim 15,

wherein after step (c) a surface-polishing step of at least a front surface is carried out, in which further smoothing of the surface is achieved using a soft polishing cloth with from 0.1 μ

m to 1 μ

m of material being removed.

22. The process as claimed in claim 15,

wherein after a step selected from the group consisting of step (c) and a surface polish which follows step (c), an epitaxial coating substantially comprising silicon is deposited at least on a front surface of the semiconductor wafer.

23. The process as claimed in claim 22,

wherein the surface of the silicon wafers is cleaned in a manner selected from the group consisting of by wet-chemical means and by the action of gases before the epitaxial coating is applied.

24. The process as claimed in claim 22,

wherein the epitaxial silicon coating is deposited at a temperature of from 900°

C. to 1250°

C.