Circuit group control system
First Claim
1. A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising:
- a command sequence specification receiving unit operable to receive, from the master processor, specification of a command sequence composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and
an execution control unit operable to cause any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in the command sequence, wherein the execution control unit includes a concurrent execution control unit operable to, while a circuit is executing a command, detect another command that can be executed by another circuit and cause the other circuit to execute the other command concurrently.
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Accused Products
Abstract
A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.
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Citations
37 Claims
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1. A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising:
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a command sequence specification receiving unit operable to receive, from the master processor, specification of a command sequence composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and
an execution control unit operable to cause any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in the command sequence, wherein the execution control unit includes a concurrent execution control unit operable to, while a circuit is executing a command, detect another command that can be executed by another circuit and cause the other circuit to execute the other command concurrently. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising:
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a command sequence specification receiving unit operable to receive from the master processor specification of a plurality of command sequences each of which is composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and
an execution control unit operable to cause any available circuits among the plurality of circuits to execute the plurality of commands in each command sequence one by one in order of arrangement, wherein the command sequence specification receiving unit includes a command storage memory, and recognizes the specification of the plurality of command sequences when the master processor writes the plurality of commands for each command sequence into the command storage memory, and the execution control unit causes any available circuits among the plurality of circuits to execute the plurality of commands for each command sequence stored in the command storage memory, one by one in order of arrangement in each command sequence. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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32. A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising:
a command sequence specification receiving unit operable to receive specification of a plurality of command sequences from the master processor, each command sequence being composed of a plurality of commands, each command being to be executed by one of the plurality of circuits;
an execution control unit operable to cause any available circuits among the plurality of circuits to execute the plurality of commands for each command sequence one by one in order of arrangement in each command sequence;
a completion notification request receiving unit operable to receive from the master processor a request to send a notification of completion of execution of a command; and
a completion notifying unit operable to, if having received from a circuit a notification of completion of execution of the command of which the master processor had requested to send a notification of completion of execution, send the notification to the master processor.
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33. A circuit group control method for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising:
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a command sequence specification receiving step for receiving, from the master processor, specification of a command sequence composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and
an execution control step for causing any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in the command sequence, wherein the execution control step includes a concurrent execution control step for, while a circuit is executing a command, detecting another command that can be executed by another circuit and causing the other circuit to execute the other command concurrently. - View Dependent Claims (34, 35)
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36. A circuit group control method for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising:
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a command sequence specification receiving step for receiving, from the master processor, specification of a plurality of command sequences each of which is composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and
an execution control step for causing any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in each command sequence.
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37. A program for referring to a memory storing a command sequence composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causing a computer to perform a circuit group control process for controlling the plurality of circuits, the circuit group control process comprising:
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a command sequence reading step for reading the command sequence from the memory;
an execution control step for causing any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in the command sequence read in the command sequence reading step, wherein the execution control step includes a concurrent execution control step for, while a circuit is executing a command, detecting another command that can be executed by another circuit and causing the other circuit to execute the other command concurrently.
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Specification