Magnetic memory device having magnetic shield layer, and manufacturing method thereof

• US 20030111626A1
• Filed: 12/12/2002
• Published: 06/19/2003
• Est. Priority Date: 12/18/2001
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosotani, Keiji
• Granted Patent: US 6,977,401 B2
• Time in Patent Office: Days
• US Class Current: 251/200
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A magnetic memory device includes a first wiring layer which runs in the first direction, a memory element which is arranged above the first wiring layer, second wiring layers which are arranged on the memory element and run in a second direction different from the first direction, and a first magnetic shield layer which is formed on the side surface of each second wiring layer and formed around the side surface of the memory element.

Claims

1. A magnetic memory device comprising:

a first wiring layer which runs in a first direction;

a memory element which is arranged above the first wiring layer;

second wiring layers which are arranged on the memory element and run in a second direction different from the first direction; and

a first magnetic shield layer which is formed on a side surface of said each second wiring layer and formed around a side surface of the memory element.

2. The device according to claim 1, wherein the first magnetic shield layer is formed on the side surface and an upper surface of said each second wiring layer and the side surface of the memory element, and is continuously formed over the second wiring layers.

3. The device according to claim 1, wherein the first magnetic shield layer includes an insulating magnetic layer.

4. The device according to claim 3, wherein the insulating magnetic layer is formed from an insulating ferrite.

5. The device according to claim 1, wherein the side surface of said each second wiring layer and the side surface of the memory element form substantially a plane, and the first magnetic shield layer is formed on the plane.

6. The device according to claim 1, wherein the memory element includes an MTJ element formed from at least a first magnetic layer, a second magnetic layer, and a nonmagnetic layer.

7. The device according to claim 6, wherein the MTJ element has either of a single junction structure having one nonmagnetic layer and a double junction structure having two nonmagnetic layers.

8. The device according to claim 6, wherein

the first and second magnetic layers have different magnetization switching thresholds, and

to write data in the MTJ element, magnetization directions of the first and second magnetic layers are set parallel to each other or anti-parallel to each other.

9. The device according to claim 6, wherein a resistance value of the MTJ element changes depending on whether magnetization directions of the first and second magnetic layers are parallel to each other or anti-parallel to each other, and data written in the MTJ element is read out in accordance with the change in resistance value.

10. The device according to claim 1, further comprising a first insulating layer which is arranged on a side surface of the memory element in the second direction and is equal in thickness to the memory element.

11. The device according to claim 1, further comprising a diode which is formed between the first wiring layer and the memory element or between the each second wiring layer and the memory element.

12. The device according to claim 1, which further comprises a transistor connected to the memory element, and in which the memory element is spaced apart from the first wiring layer.

13. The device according to claim 1, further comprising a second magnetic shield layer formed on an upper surface of said each second wiring layer.

14. The device according to claim 13, wherein the first magnetic shield layer includes an insulating magnetic layer.

15. The device according to claim 13, wherein the second magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

16. The device according to claim 1, further comprising:

a second magnetic shield layer formed on an upper surface of said each second wiring layer; and

a second insulating layer formed between the side surface of said each second wiring layer and the side surface of the memory element on the one hand and the first magnetic shield layer on the other hand.

17. The device according to claim 16, wherein the first magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

18. The device according to claim 16, wherein the second magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

19. The device according to claim 16, wherein the first magnetic shield layer is formed on a side surface of the second insulating layer and an upper surface of the second magnetic shield layer, and is continuously formed over the second wiring layers.

20. The device according to claim 19, wherein

the second magnetic shield layer includes an insulating magnetic layer, and

the first magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

21. The device according to claim 19, wherein

the second magnetic shield layer includes a conductive magnetic layer, and

the first magnetic shield layer includes an insulating magnetic layer.

22. The device according to claim 1, further comprising a third insulating layer which is formed between the side surface of the memory element and the first magnetic shield layer, a side surface of the third insulating layer being substantially parallel to the side surface of the second wiring layer.

23. The device according to claim 22, wherein a width of the memory element in the first direction is smaller than a width of said each second wiring layer.

24. The device according to claim 22, wherein the first magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

25. The device according to claim 22, wherein the first magnetic shield layer is formed on the side surface and an upper surface of said each second wiring layer and the side surface of the third insulating layer, and is continuously formed between the second wiring layers.

26. The device according to claim 25, wherein the first magnetic shield layer includes an insulating magnetic layer.

27. The device according to claim 22, further comprising a second magnetic shield layer which is formed on an upper surface of said each second wiring layer.

28. The device according to claim 27, wherein the first magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

29. The device according to claim 27, wherein the second magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

30. The device according to claim 1, further comprising a third magnetic shield layer which is formed on a lower surface and a side surface of the first wiring layer.

31. The device according to claim 30, wherein the third magnetic shield layer includes either of an insulating magnetic layer and a conductive magnetic layer.

32. The device according to claim 1, further comprising first and second barrier metal layers which sandwich the first magnetic shield layer.

33. The device according to claim 30, further comprising third and fourth barrier metal layers which sandwich the third magnetic shield layer.

34. The device according to claim 1, further comprising a third wiring layer which is arranged on the same plane as the first wiring layer, runs parallel to the first wiring layer, is connected to the memory element, and is used as a read wiring line.

35. The device according to claim 1, further comprising a fourth wiring layer which is arranged between the first wiring layer and the memory element, runs parallel to the first wiring layer, is connected to the memory element, and is used as a read wiring line.

36. A magnetic memory device manufacturing method, comprising:

forming a first wiring layer which runs in a first direction;

selectively forming a memory element above the first wiring layer;

forming a first insulating layer around the memory element;

forming, on the first insulating layer and the memory element, second wiring layers which run in a second direction different from the first direction;

removing a portion of the first insulating layer not covered with the second wiring layers by using the second wiring layers as a mask; and

forming a first magnetic shield layer over the second wiring layers to cover the first and second wiring layers and the memory element.

37. The method according to claim 36, wherein the first magnetic shield layer is formed with a film thickness not more than ½

a distance between the second wiring layers.

38. The method according to claim 36, wherein the memory element includes an MTJ element formed from at least a first magnetic layer, a second magnetic layer, and a nonmagnetic layer.

39. The method according to claim 36, further comprising forming a diode between the first wiring layer and the memory element or between the each second wiring layer and the memory element.

40. The method according to claim 36, further comprising forming a transistor to be connected to the memory element.

41. The method according to claim 36, further comprising, after forming the first magnetic shield layer, removing the first magnetic shield layer from an upper surface of said each second wiring layer and from between the second wiring layers to leave the first magnetic shield layer on a side surface of said each second wiring layer and a side surface of the memory element.

42. The method according to claim 41, wherein the first magnetic shield layer is removed by anisotropic etching.

43. The method according to claim 36, further comprising:

before forming the first magnetic shield layer, forming a second magnetic shield layer on an upper surface of said each second wiring layer; and

after forming the first magnetic shield layer, removing a selected portion of the first magnetic shield layer to leave the first magnetic shield layer on a side surface of said each second wiring layer and a side surface of the memory element.

44. The method according to claim 36, further comprising, before forming the first magnetic shield layer:

forming a second magnetic shield layer on an upper surface of said each second wiring layer; and

forming a second insulating layer on a side surface of said each second wiring layer and a side surface of the memory element.

45. The method according to claim 44, further comprising, after forming the first magnetic shield layer, removing the first magnetic shield layer from an upper surface of the second magnetic shield layer and from between the second wiring layers to leave the first magnetic shield layer on a side surface of the second insulating layer.

46. The method according to claim 36, wherein

the second wiring layers are formed with a width of said each second wiring layer set larger than a width of the memory element in the first direction,

a portion of the first insulating layer not covered with the second wiring layers is removed using the second wiring layers as a mask to leave the first insulating layer on a side surface of the memory element that is recessed from a side surface of said each second wiring layer, and

the first magnetic shield layer is formed on the side surface and an upper surface of said each second wiring layer and a side surface of the first insulating layer.

47. The method according to claim 46, further comprising, after forming the first magnetic shield layer, removing the first magnetic shield layer from an upper surface of a second magnetic shield layer and from between the second wiring layers to leave the first magnetic shield layer on the side surface of the first insulating layer and the side surface of said each second wiring layer.

48. The method according to claim 47, further comprising, before forming the first magnetic shield layer, forming the second magnetic shield layer on the upper surface of said each second wiring layer.

49. A magnetic memory device manufacturing method, comprising:

forming a first wiring layer which runs in a first direction;

forming above the first wiring layer a straight memory element which runs in the first direction;

forming a first insulating layer around the memory element;

forming, on the first insulating layer and the memory element, second wiring layers which run in a second direction different from the first direction;

removing portions of the first insulating layer and the memory element which are not covered with the second wiring layers by using the second wiring layers as a mask to form the memory element into an island shape; and

forming a first magnetic shield layer over the second wiring layers.