Phase splitter circuit with clock duty/skew correction function

• US 20030111705A1
• Filed: 09/12/2002
• Published: 06/19/2003
• Est. Priority Date: 12/18/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Hee-Young
• Granted Patent: US 6,680,637 B2
• Time in Patent Office: Days
• US Class Current: 257/491
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A phase splitter circuit includes a first signal transfer path for recieving an input signal to output a first output signal, a second signal transfer path for receiving the input signal to output a second output signal having an inverted phase of the first output signal, and a duty cycle correction circuit for controlling pull-up and pull-down speeds of the first and second signal transfer paths to the opposite direction in response to the first and second output signals. According to this structure, duty cycles of the first and second output signals approach 50% and a skew or delay time therebetween approaches “0.”

Claims

1. A phase splitter circuit comprising:

a first signal transfer path for receiving an input signal to output a first output signal;

a second signal transfer path for receiving the input signal to output a second output signal with an inverted phase with respect to the first output signal; and

a duty cycle correction circuit operating responsive to the first and second output signals,

wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second signal transfer paths to opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.

2. The phase splitter circuit of claim 1, wherein the input signal is one selected from a clock signal and a data signal.

3. The phase splitter circuit of claim 1, wherein the first signal transfer path comprises first and second inverters that are serially coupled between the input signal and the first output signal, and the second signal transfer path comprises third, fourth, and fifth inverters that are serially coupled between the input signal and the second output signal.

4. The phase splitter circuit of claim 3, wherein the duty cycle correction circuit charges or discharges a control node in response to the first and second output signals, and pull-up and pull-down speeds of the first inverter are adjusted according to a potential of the control node, and pull-up and pull-down speeds of the fourth inverter are adjusted according to an inverted potential of the control node.

5. The phase splitter circuit of claim 4, wherein the duty cycle correction circuit adjusts the pull-up speed of the first inverter in an increasing direction and the pull-down speed of the first inverter in a decreasing direction when the potential of the control node is lowered relative to a previous potential thereof;

and

wherein the duty cycle correction circuit adjusts the pull-up speed of the fourth inverter in the decreasing direction and the pull-down speed of the fourth inverter in the increasing direction when the inverted potential of the control node is increased relative to a previous potential thereof.

6. The phase splitter circuit of claim 5, wherein the first and fourth inverters comprises a stack inverter having first pull-up and pull-down transistors controlled by the potential of the control node and second pull-up and pull-down transistors controlled by an input signal of a corresponding inverter.

7. The phase splitter circuit of claim 6, wherein when a potential of the control node is relatively decreased and the input signal transitions from a low level to a high level, a high-to-low transition of an output signal of the first inverter becomes relatively slower, and when a potential of the control node is relatively decreased and the input signal transitions from the high level to the low level, a low-to-high transition of the output signal of the first inverter becomes relatively faster.

8. The phase splitter circuit of claim 6, wherein when an inverted potential of the control node is relatively increased and an input signal of the fourth inverter transitions from a high level to a low level, a low-to-high transition of an output signal of the fourth inverter becomes relatively slower, and when the inverted potential of the control node is relatively decreased and the input signal of the fourth inverter transitions from the low level to the high level, a high-to-low transition of the output signal of the fourth inverter becomes relatively faster.

9. The phase splitter of claim 4, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to the first output signal;

a pull-down transistor for pulling down the control node in response to an inverted version of the second output signal;

a feedback capacitor coupled between the control node and ground voltage; and

an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.

10. The phase splitter circuit of claim 4, wherein the duty cycle correction circuit comprises:

first and second pull-up transistors for pulling up the control node in response to the first output signal and a first control signal, the first and second pull-up transistors being serially coupled between a power supply voltage and the control node;

first and second pull-down transistors for pulling down the control node in response to an inverted version of the second output signal and a second control signal, the first and second pull-down transistors being serially coupled between the power supply voltage and the control node;

a feedback capacitor coupled between the control node and the ground voltage; and

an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.

11. The phase splitter circuit of claim 3, wherein the duty cycle correction circuit charges or discharges a control node in response to the first and second output signals, and the pull-up and pull-down speeds of the respective first and third inverters are adjusted according to the potential of the control node.

12. The phase splitter of claim 11, wherein the duty cycle correction circuit adjusts the pull-up speed of the respective first and second inverters in an increasing direction and the pull-down speed of the respective first and third inverters in a decreasing direction when the potential of the control node is reduced relative to a previous potential thereof.

13. The phase splitter circuit of claim 11, wherein the first and third inverters comprise a stack inverter having first pull-up and pull-down transistors controlled by the potential of the control node and second pull-up and pull-down transistors controlled by an input signal of a corresponding inverter.

14. The phase splitter circuit of claim 13, wherein when a potential of the control node is relatively decreased and the input signal transitions from a low level to a high level, a high-to-low transition of an output signal of the respective first and third inverters becomes relatively slower, and when a potential of the control node is relatively reduced and the input signal transitions from the high level to the low level, a low-to-high transition of the output signal of the respective first and third inverters becomes relatively faster.

15. The phase splitter circuit of claim 11, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to the first output signal;

a pull-down transistor for pulling down the control node in response to an inverted version of the second output signal; and

a feedback capacitor coupled between the control node and a ground voltage.

16. The phase splitter circuit of claim 11, wherein the duty cycle correction circuit comprises:

first and second pull-up transistors for pulling up the control node in response to the first output signal and a first control signal, the first and second pull-up transistors being serially coupled between a power supply voltage and the control node;

first and second pull-down transistors for pulling down the control node in response to an inverted version of the second output signal and a second control signal, the first and second pull-down transistors being serially coupled between the control node and a ground voltage; and

a feedback capacitor coupled between the control node and the ground voltage.

17. A phase splitter circuit comprising:

a first stack inverter for inverting an input signal;

a first inverter for inverting an output signal of the first stack inverter to output a first output signal;

a second inverter for inverting the input signal;

a second stack inverter for inverting an output signal of the second inverter;

a third inverter for inverting an output signal of the second stack inverter to output a second output signal; and

a duty cycle correction circuit for controlling the first and second stack inverters in response to the first and second output signals,

wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.

18. The phase splitter circuit of claim 17, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to the first output signal;

a pull-down transistor for pulling down the control node in response to an inverted version of the second output signal;

a feedback capacitor coupled between the control node and a ground voltage; and

an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.

19. The phase splitter circuit of claim 17, wherein the duty cycle correction circuit comprises:

first and second pull-up transistors for pulling up the control node in response to the first output signal and a first control circuit, the first and second pull-up transistors being serially coupled between a power supply voltage and the control node;

first and second pull-down transistors for pulling down the control node in response to an inverted version of the second output signal and a second control signal, the first and second pull-down transistors being serially coupled between the control node and a ground voltage;

a feedback capacitor coupled between the control node and the ground voltage; and

an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.

20. A phase splitter comprising:

a first stack inverter for inverting an input signal;

a first inverter for inverting an output signal of the first stack inverter to output a first output signal;

a second stack inverter for inverting the input signal;

a second inverter for inverting an output signal of the second stack inverter;

a third inverter for inverting an output signal of the second inverter to output a second output signal; and

a duty cycle correction circuit for controlling the first and second stack inverters in response to the first and second output signals,

wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.

21. The phase splitter circuit of claim 20, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling the control node in response to the first output signal;

a pull-down transistor for pulling down the control node in response to an inverted version of the second output signal; and

a feedback capacitor coupled between the control node and a ground voltage.

22. The phase splitter circuit of claim 20, wherein the duty cycle correction circuit comprises:

first and second pull-up transistors for pulling up the control node I response to the first output signal and a first control signal, the first and second pull-up transistors being serially coupled between a power supply voltage and the control node;

first and second pull-down transistors for pulling down the control node in response to an inverted version of the second output signal and a second control signal, the first and second pull-down transistors being serially coupled between the control node and a ground voltage; and

a feedback capacitor coupled between the control node and the ground voltage.

23. A phase splitter circuit comprising:

a first stack inverter for inverting an input signal;

a first inverter for inverting an output signal of the first stack inverter to output a first output signal;

a second inverter for inverting the input signal;

a second stack inverter for inverting an output signal of the second inverter;

a third inverter for inverting an output signal of the second stack inverter to output a second inverter; and

a duty cycle correction circuit for controlling the first and second stack inverters in response to either one of the first and second output signals,

wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to either one of the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.

24. The phase splitter circuit of claim 23, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to the first output signal;

a pull-down transistor for pulling down the control node in response to the first output signal;

a feedback capacitor coupled between the control node and a ground voltage; and

an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.

25. The phase splitter circuit of claim 23, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to an inverted version of the second output signal;

a pull-down transistor for pulling down the control node in response to the inverted version of the second output signal;

a feedback capacitor coupled between the control node and a ground voltage; and

an inverting amplifier for inverting a potential of the control node to output the inverted potential of the control node.

26. A phase splitter circuit comprising:

a first stack inverter for inverting an input signal;

a first inverter for inverting an output signal of the first stack inverter to output a first output signal;

a second stack inverter for inverting the input signal;

a second inverter for inverting an output signal of the second stack inverter;

a third inverter for inverting an output signal of the second inverter to output a second output signal; and

a duty cycle correction circuit for controlling the first and second stack inverter in response to either one of the first and second output signals,

wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to either one of the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.

27. The phase splitter circuit of claim 26, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to the first output signal;

a pull-down transistor for pulling down the control node in response to the first output signal; and

a feedback capacitor coupled between the control node and a ground voltage.

28. The phase splitter circuit of claim 26, wherein the duty cycle correction circuit comprises:

a pull-up transistor for pulling up the control node in response to an inverted version of the second output signal;

a pull-down transistor for pulling down the control node in response to the inverted version of the second output signal; and

a feedback capacitor coupled between the control node and a ground voltage.