Phase splitter circuit with clock duty/skew correction function
First Claim
Patent Images
1. A phase splitter circuit comprising:
- a first signal transfer path for receiving an input signal to output a first output signal;
a second signal transfer path for receiving the input signal to output a second output signal with an inverted phase with respect to the first output signal; and
a duty cycle correction circuit operating responsive to the first and second output signals, wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second signal transfer paths to opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle.
1 Assignment
0 Petitions
Accused Products
Abstract
A phase splitter circuit includes a first signal transfer path for recieving an input signal to output a first output signal, a second signal transfer path for receiving the input signal to output a second output signal having an inverted phase of the first output signal, and a duty cycle correction circuit for controlling pull-up and pull-down speeds of the first and second signal transfer paths to the opposite direction in response to the first and second output signals. According to this structure, duty cycles of the first and second output signals approach 50% and a skew or delay time therebetween approaches “0.”
-
Citations
28 Claims
-
1. A phase splitter circuit comprising:
-
a first signal transfer path for receiving an input signal to output a first output signal;
a second signal transfer path for receiving the input signal to output a second output signal with an inverted phase with respect to the first output signal; and
a duty cycle correction circuit operating responsive to the first and second output signals, wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second signal transfer paths to opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A phase splitter circuit comprising:
-
a first stack inverter for inverting an input signal;
a first inverter for inverting an output signal of the first stack inverter to output a first output signal;
a second inverter for inverting the input signal;
a second stack inverter for inverting an output signal of the second inverter;
a third inverter for inverting an output signal of the second stack inverter to output a second output signal; and
a duty cycle correction circuit for controlling the first and second stack inverters in response to the first and second output signals, wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle. - View Dependent Claims (18, 19)
-
-
20. A phase splitter comprising:
-
a first stack inverter for inverting an input signal;
a first inverter for inverting an output signal of the first stack inverter to output a first output signal;
a second stack inverter for inverting the input signal;
a second inverter for inverting an output signal of the second stack inverter;
a third inverter for inverting an output signal of the second inverter to output a second output signal; and
a duty cycle correction circuit for controlling the first and second stack inverters in response to the first and second output signals, wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle. - View Dependent Claims (21, 22)
-
-
23. A phase splitter circuit comprising:
-
a first stack inverter for inverting an input signal;
a first inverter for inverting an output signal of the first stack inverter to output a first output signal;
a second inverter for inverting the input signal;
a second stack inverter for inverting an output signal of the second inverter;
a third inverter for inverting an output signal of the second stack inverter to output a second inverter; and
a duty cycle correction circuit for controlling the first and second stack inverters in response to either one of the first and second output signals, wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to either one of the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle. - View Dependent Claims (24, 25)
-
-
26. A phase splitter circuit comprising:
-
a first stack inverter for inverting an input signal;
a first inverter for inverting an output signal of the first stack inverter to output a first output signal;
a second stack inverter for inverting the input signal;
a second inverter for inverting an output signal of the second stack inverter;
a third inverter for inverting an output signal of the second inverter to output a second output signal; and
a duty cycle correction circuit for controlling the first and second stack inverter in response to either one of the first and second output signals, wherein the duty cycle correction circuit controls pull-up and pull-down speeds of the first and second stack inverters in opposite directions in response to either one of the first and second output signals so that each of the first and second output signals has a half duty cycle when a duty cycle of the input signal or of the respective first and second output signals deviates from the half duty cycle. - View Dependent Claims (27, 28)
-
Specification