Flat panel display device with face plate and method for fabricating the same

• US 20030111954A1
• Filed: 11/13/2002
• Published: 06/19/2003
• Est. Priority Date: 12/14/2001
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: Koo, Jae-Bon, Shin, Dong-Chan
• Granted Patent: US 7,173,372 B2
• Time in Patent Office: Days
• US Class Current: 313/498
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A flat panel display device which is capable of preventing in-line shorts by forming as a face plate a common power line impressing an equal power supply to all pixels. The flat panel display includes a power supply layer formed on an insulation substrate and connected with source/drain electrodes through contact holes; and an insulating layer formed with a contact hole to insulate the power supply layer and a thin film transistor, wherein the thin film transistor is formed over the insulating layer and includes the source/drain electrodes.

Claims

1. A flat panel display device comprising:

a power supply layer formed on an insulation substrate and connected with source/drain electrodes through contact holes; and

an insulating layer formed with a contact hole to insulate the power supply layer and a thin film transistor, wherein the thin film transistor is formed over the insulating layer and includes the source/drain electrodes.

2. The flat panel display device according to claim 1, wherein the power supply layer comprises an opaque conductive material having a low resistance.

3. The flat panel display device according to claim 1, wherein the power supply layer comprises a transparent conductive material having a low resistance.

4. The flat panel display device according to claim 1, wherein the power supply layer has a face plate shape.

5. The flat panel display device according to claim 1, wherein the power supply layer has a patterned shape with an empty region corresponding to an area of the thin film transistor.

6. The flat panel display device according to claim 1, wherein the power supply layer is electrically connected to each pixel through one corresponding contact hole among a plurality of contact holes, wherein a common voltage is supplied to the source/drain electrodes of the thin film transistor from the power supply layer.

7. A method of fabricating a flat panel display device, comprising

forming a power supply layer on an insulation substrate;

forming an insulating layer on the power supply layer;

forming a contact hole exposing a portion of the power supply layer by etching the insulating layer; and

forming an island shaped conductive pattern connected to the power supply layer through the contact hole.

8. The method according to claim 7, wherein the island shaped conductive pattern functions as a source/drain electrode of a thin film transistor and an electrode of a capacitor.

9. The method according to claim 8, wherein a part of the power supply layer corresponding to the thin film transistor is patterned so as to remove an effect of backside bias.

10. The method according to claim 7, wherein the power supply layer comprises an opaque conductive material having a low resistance.

11. The method according to claim 7, wherein the power supply layer comprises a transparent conductive material having a low resistance.

12. A method of fabricating a flat panel display device, comprising:

providing an insulation substrate having a first and second region;

forming a power supply layer on the insulation substrate;

forming a buffer layer on the power supply layer;

forming a semiconductor layer on the buffer layer in the second region of the insulation substrate;

forming a gate insulating layer enclosing the semiconductor layer;

forming a gate and a first electrode of a capacitor simultaneously on the gate insulating layer;

forming source and drain regions in the semiconductor layer;

forming an interlayer insulating layer on the gate insulating layer enclosing the gate and the first electrode of the capacitor;

simultaneously forming first and second contact holes in the interlayer insulating layer to expose a portion of the power supply layer; and

forming source and drain electrodes contacting the source and drain regions through the first and second contact holes, respectively, by patterning the interlayer insulating layer after depositing source and drain electrode materials on the interlayer insulating layer.

13. The method according to claim 12, wherein the source and drain regions are formed by ion implanting one of n-type and p-type impurities into the semiconductor layer such that a part of the semiconductor layer below the gate acts as a channel layer.

14. The method according to claim 12, wherein the first and second contact holes are formed by etching the interlayer insulating layer.

15. The method according to claim 14, further comprising forming a passivation layer on the interlayer insulating layer, the source and drain electrodes and the second electrode of the capacitor with a via hole exposing a portion of one of the source and drain electrodes.

16. The method according to claim 15, further comprising forming a pixel electrode on the passivation layer such that the pixel electrode is connected to the drain electrode through a via hole.

17. The method according to claim 16, further comprising forming a planarization layer on the passivation layer and enclosing the pixel electrode.

18. The method according to claim 17, further comprising:

forming an opening part by exposing a portion of the pixel layer;

forming an EL layer in the opening part; and

forming a cathode electrode on the EL layer as a transparent electrode.

20. The method according to claim 18, wherein the exposing a portion of the piexel layer is performed by etching the planarization layer.