Low drop-out voltage regulator with power supply rejection boost circuit

• US 20030111987A1
• Filed: 12/09/2002
• Published: 06/19/2003
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chen, Jun, Hoon, Siew K.
• Granted Patent: US 6,897,637 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted between the pass element 20 and the amplifier 26 of the low drop-out regulator. The voltage regulator circuit includes a pass element 20 coupled between an input node and an output node; a voltage feedback circuit 28 and 30 coupled to the output node Vo; an amplifier 26 having an input coupled to the voltage feedback circuit; and a voltage subtractor 36 having a control node coupled to an output of the amplifier 26, an output coupled to a control node of the pass element 20, and an input coupled to the input node. The boost circuit improves supply noise rejection performance significantly without adding much complexity to the regulator system. The boost circuit is simple and consumes negligible silicon area and power.

Claims

1. A circuit comprising:

a pass element coupled between an input node and an output node;

a voltage feedback circuit coupled to the output node;

an amplifier having an input coupled to the voltage feedback circuit;

a voltage subtractor having a control node coupled to an output of the amplifier, an output coupled to a control node of the pass element, and an input coupled to the input node.

2. The circuit of claim 1 wherein the pass element is a transistor.

3. The circuit of claim 1 wherein the pass element is a MOS transistor.

4. The circuit of claim 1 wherein the pass element is a PMOS transistor.

5. The circuit of claim 1 wherein the voltage subtractor comprises:

a first transistor coupled to the control node of the pass element, and a control node of the first transistor coupled to the output of the amplifier; and

a second transistor coupled between the control node of the pass element and the input node.

6. The circuit of claim 5 wherein a control node of the second transistor is coupled to the input node.

7. The circuit of claim 6 wherein the first and second transistors are NMOS transistors.

8. The circuit of claim 5 wherein a control node of the second transistor is coupled to the control node of the pass element.

9. The circuit of claim 8 wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

10. The circuit of claim 1 wherein the feedback circuit is a resistor divider circuit.

11. The circuit of claim 1 wherein the feedback circuit comprises:

a first resistor coupled between the output node and the input of the amplifier; and

a second resistor coupled between the input of the amplifier and a common node.

12. The circuit of claim 1 further comprising a voltage reference coupled to a second input of the amplifier.

13. A low drop-out voltage regulator circuit comprising:

a pass transistor coupled between an input node and an output node;

a resistor divider having an input coupled to the input node;

an amplifier having a first input coupled to an output of the resistor divider;

a voltage subtractor coupled between the input node and a control node of the pass transistor, and an input of the voltage subtractor coupled to an output of the amplifier.

14. The circuit of claim 13 wherein the voltage subtractor comprises:

a first transistor coupled to the control node of the pass transistor, and a control node of the first transistor coupled to the output of the amplifier; and

a second transistor coupled between the control node of the pass transistor and the input node.

15. The circuit of claim 14 wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

16. The circuit of claim 14 wherein the first and second transistors are NMOS transistors.

17. The circuit of claim 13 wherein the resistor divider comprises:

a first resistor coupled between the output node and the input of the amplifier; and

a second resistor coupled between the input of the amplifier and a common node.

18. The circuit of claim 13 further comprising a reference voltage coupled to a second input of the amplifier.

19. The circuit of claim 13 wherein the pass transistor is a MOS transistor.

20. The circuit of claim 13 wherein the pass transistor is a PMOS transistor.