Process for producing high performance interconnects

• US 20030112576A1
• Filed: 09/26/2002
• Published: 06/19/2003
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Brewer, Peter D., Pobanz, Carl W.
• Granted Patent: US 7,351,660 B2
• Time in Patent Office: Days
• US Class Current: 361/119
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10335 : Indium phosphide [InP]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

A method for fabricating high performance vertical and horizontal electrical connections in a three dimensional semiconductor structure. A dielectric film is imprinted with a stamp pattern at high vacuum and with precise temperature and stamping pressure control. The stamp pattern may be formed on a substrate using semiconductor fabrication techniques. After the dielectric film is stamped, residual dielectric film is removed to allow access to an underlying layer. Via and trench regions formed within the dielectric film by stamping are then metalized to provide the high performance interconnections. Multiple layers of interconnections in the three dimensional structure are provided by stacking layers of stamped and metalized dielectric films on top of each other.

Claims

1. A method for producing electrical interconnections in a three dimensional semiconductor structure, comprising the steps of:

(a) applying a dielectric film to a top portion of the three dimensional semiconductor structure;

(b) providing a stamp substrate;

(c) etching the stamp substrate to create a stamp pattern with raised areas;

(d) aligning the stamp substrate to the dielectric film;

(e) imprinting the dielectric film with the stamp pattern on the stamp substrate so as to create via regions and/or trench regions in the dielectric film;

(f) removing residual film from the via and/or trench regions of the dielectric film; and

(g) metallizing the via and/or trench regions of the dielectric film to provide electrical interconnections.

2. The method according to claim 1, further comprising the steps of

(h) applying another layer of dielectric film on the top portion of the three dimensional semiconductor structure;

and

(i) repeating steps (c)-(g) for each additional layer of dielectric film applied.

3. The method according to claim 1 further comprising the step of coating the stamp substrate with a release agent prior to performing the step of imprinting the dielectric film.

4. The method according to claim 1 wherein the step of applying a dielectric film comprises spinning on the dielectric film with a photoresist spinner.

5. The method according to claim 1 wherein the step of applying a dielectric film comprises bonding a sheet of dielectric film.

6. The method according to claim 1 wherein the step of imprinting the dielectric film comprises molding the dielectric film under high vacuum conditions with precise temperature and imprinting pressure control.

7. The method according to claim 1 wherein the step of imprinting the dielectric film further comprises the step of hardening the dielectric film by baking the dielectric film.

8. The method according to claim 1 wherein the step of imprinting the dielectric film further comprises the step of hardening the dielectric film by exposing the dielectric film to ultraviolet light.

9. The method according to claim 1 wherein the step of removing residual film comprises the steps of:

patterning the dielectric film with photoresist, and

plasma etching the dielectric film.

10. The method according to claim 1 wherein the step of removing residual film comprises the steps of:

patterning the dielectric film with photoresist, and

laser ablating the residual film.

11. The method according to claim 1 wherein the step of metallizing the via and/or trench regions comprises vacuum depositing metal films.

12. The method according to claim 11 wherein the metal films comprise one or more of the metals from the group consisting of titanium, gold, chromium, nickel, platinum, and aluminum.

13. A method for producing high performance electrical interconnections in a three dimensional semiconductor structure, comprising the steps of:

(a) providing a stamp substrate;

(b) etching the stamp substrate to create a stamp pattern with raised areas;

(c) providing a dielectric film;

(d) aligning the stamp substrate to the dielectric film;

(e) imprinting the dielectric film with the stamp pattern on the stamp substrate so as to create via regions and/or trench regions in the dielectric film;

(f) aligning the dielectric film to a top portion of the three dimensional semiconductor structure;

(g) bonding the dielectric film to the three dimensional semiconductor structure;

(h) removing residual film from the via and/or trench regions of the dielectric film; and

(i) metallizing the via and/or trench regions of the dielectric film.

14. The method according to claim 13 wherein steps (b)-(i) are repeated to form a multiple layer structure.

15. The method according to claim 13 wherein the step of imprinting the dielectric film comprises molding the dielectric film under high vacuum conditions with precise temperature and imprinting pressure control.

16. The method according to claim 13 wherein the step of imprinting the dielectric film further comprises the step of hardening the dielectric film by baking the dielectric film.

17. The method according to claim 13 wherein the step of imprinting the dielectric film further comprises the step of hardening the dielectric film by exposing the dielectric film to ultraviolet light.

18. The method according to claim 13 wherein the step of removing residual film comprises the steps of:

patterning the dielectric film with photoresist, and

plasma etching the dielectric film.

19. The method according to claim 13 wherein the step of removing residual film comprises the steps of:

patterning the dielectric film with photoresist, and

laser ablating the residual film.

20. The method according to claim 13 wherein the step of metallizing the via and/or trench regions comprises vacuum depositing metal films.

21. The method according to claim 20 wherein the metal films comprise one or more of the metals from the group consisting of titanium, gold, chromium, nickel, platinum, and aluminum.

22. A method for forming coplanar interconnects between layers in a multiple layer three dimensional structure, the method comprising:

forming one or more lower layer metal lines on a lower layer;

depositing a polymer layer on top of the metal lines on the lower layer;

forming via holes in the polymer layer directly above the metal lines on the lower layer;

metallizing the via holes to provide vertical electrical connections to the lower layer metal lines; and

,

forming one or more upper layer metal lines on top of the polymer layer, the one or more upper layer metal lines electrically connecting to the vertical electrical connections.

23. The method according to claim 22, wherein the step of forming via holes comprises:

providing a stamp substrate;

etching the stamp substrate to create a stamp pattern with raised areas corresponding to the via holes;

aligning the stamp substrate to the polymer layer;

imprinting the polymer layer with the stamp pattern on the stamp substrate so as to create the via holes; and

removing residual polymer from the via holes.

24. A method for forming a coaxial connection between layers in a multiple layer three dimensional structure, the method comprising:

forming a coaxial line structure on a lower layer, the coaxial line structure comprising a pair of lower layer metal shield lines with a lower layer center conductor line disposed between the lower layer metal shield lines and electrically isolated from the lower layer metal shield lines;

depositing a first polymer layer on top of the coaxial line structure on the lower layer;

forming a center conductor recess and a ground shield recess in the first polymer layer directly above the coaxial line structure on the lower layer, the center conductor recess formed above the lower layer center conductor line at one end of the lower layer center conductor line and the ground shield recess formed above ends of the pair of lower layer metal shield lines adjacent to the end of the lower layer center conductor line, the ground shield recess substantially surrounding the center conductor recess; and

,

metallizing the center conductor recess and the ground shield recess to provide a vertical center conductor and a vertical ground shield, the vertical center conductor being in electrical connection with the lower layer center conductor and the vertical ground shield in electrical connection with the lower layer metal shield lines.

25. The method according to claim 24, further comprising the steps of:

depositing a metal ground layer on top of the first polymer layer, the metal ground layer in electrical connection with the vertical ground shield;

removing metal from the metal ground layer above the vertical center conductor to form an open area in the metal layer with a greater diameter than the vertical center conductor;

depositing a second polymer layer on top of the metal ground layer;

forming a via hole in the second polymer layer above the vertical center conductor; and

metallizing the via hole to provide a second vertical connection to the vertical center conductor.

26. The method according to claim 25, further comprising the step of depositing a patch antenna metal structure on top of the second polymer layer, the patch antenna metal structure being electrically connected at one end of the second vertical connection.

27. The method according to claim 24, wherein the step of forming a center conductor recess and a ground shield recess comprises:

providing a stamp substrate;

etching the stamp substrate to create a stamp pattern with raised areas corresponding to the center conductor recess and the ground shield recess;

aligning the stamp substrate to the first polymer layer;

imprinting the first polymer layer with the stamp pattern on the stamp substrate so as to create the center conductor recess and the ground shield recess; and

removing residual polymer from the center conductor recess and the ground shield recess.

28. A method for forming shielded horizontal transmission line interconnections between layers in a multiple layer three dimensional structure, the method comprising:

depositing a lower metal layer on a lower layer containing one or more lower level metal interconnects, each lower level interconnect being electrically connected to the lower metal layer at a lower connect area;

removing metal from the lower metal layer around each lower connect area to form insulating gaps between each lower connect area and the lower metal layer;

depositing a first polymer layer on top of the lower metal layer;

forming vertical shield recesses and horizontal interconnect recesses in the first polymer layer, the vertical shield recesses being formed above and contacting areas of the metal layer adjacent to the insulating gaps and each vertical shield recess projecting in a horizontal direction in the first polymer layer parallel to each other vertical shield recess, and each horizontal interconnect recess having one end formed above and contacting one of the lower contact areas and having a horizontal trench formed between the vertical shield recesses with a first end and a second end, the first end of the horizontal trench at the end of the horizontal interconnect recess above the lower connect area;

metallizing the vertical shield recesses to form vertical shields in electrical contact with the lower metal layer;

metallizing the horizontal interconnect recesses to form horizontal interconnects, each horizontal interconnect having a first end in electrical contact with one of the lower contact areas and a second end, the horizontal interconnects having a height less than a height of the horizontal interconnect recesses;

depositing a second polymer layer to form insulating sections above the horizontal interconnects;

depositing an upper metal layer on top of the first polymer layer, the upper metal layer being in electrical contact with the vertical shields;

removing metal from the upper metal layer above the second end of each horizontal interconnect to form upper interconnect holes;

depositing a third polymer layer on the upper metal layer and in the upper interconnect holes;

forming upper interconnect recesses in the second polymer layer above the second end of each horizontal interconnect and in the third polymer layer above and through the upper interconnect holes;

metallizing the upper interconnect recesses to form upper vertical interconnects.

29. The method according to claim 28, wherein the step of forming vertical shield recesses and horizontal interconnect recesses comprises:

providing a stamp substrate;

etching the stamp substrate to create a stamp pattern with raised areas corresponding to the vertical shield recesses and horizontal interconnect recesses;

aligning the stamp substrate to the first polymer layer;

imprinting the first polymer layer with the stamp pattern on the stamp substrate so as to create the vertical shield recesses and horizontal interconnect recesses; and

removing residual polymer from the vertical shield recesses and horizontal interconnect recesses.