METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT

• US 20030113963A1
• Filed: 07/24/2002
• Published: 06/19/2003
• Est. Priority Date: 07/24/2001
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Wurzer, Helmut
• Granted Patent: US 6,613,624 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits having both a memory region and a logic region are fabricated either with different dopings for pMOS and nMOS transistors in the logic region (dual work function) or with a common source/drain electrode in the memory region (borderless contact). In the latter case, all the transistors of the semiconductor circuit receive the same gate doping. A method is proposed by which it is possible to realize dual work function and borderless contact on a semiconductor substrate simultaneously in a simple manner.

Claims

1. A method for fabricating an integrated semiconductor circuit, which comprises:

depositing a first layer sequence onto a semiconductor substrate, the first layer sequence having a bottommost layer composed of an oxidizable material;

patterning the first layer sequence by anisotropic etching in a first area region of the semiconductor substrate to form first gate structures having sidewalls and top sides, surfaces of the semiconductor substrate lying parallel to the top sides being defined between the gate structures, and removing the first layer sequence in a second area region of the semiconductor substrate;

oxidizing the bottommost layer of the first layer sequence at the sidewalls of the first gate structures in the first area region;

covering, in the first area region, at least the top sides of the first gate structures and the surfaces of the semiconductor substrate with an etch stop layer;

covering the first gate structures of the first area region by depositing a second layer sequence onto the semiconductor substrate;

patterning the second layer sequence by anisotropic etching of the second layer sequence to form second gate structures in the second area region and removing the second layer sequence from the first gate structures in the first area region, and stopping the removing of the second layer sequence in the first area region with the etch stop layer.

2. The method according to claim 1, which further comprises:

in the depositing step, depositing a first etch stop layer covering the top sides of the first gate structures as topmost layer of the first layer sequence; and

in the oxidizing step, producing an oxide layer as a further etch stop layer on the surfaces of the semiconductor substrate.

3. The method according to claim 1, which further comprises, between the oxidizing step and the covering step, depositing an additional layer as an etch stop layer onto the first area region.

4. The method according to claim 1, which further comprises using a nitride as the etch stop layer.

5. The method according to claim 4, which further comprises using a silicon nitride as the etching layer.

6. The method according to claim 1, which further comprises using a metal oxide as the etch stop layer.

7. The method according to claim 6, which further comprises using tungsten oxide as the etch stop layer.

8. The method according to claim 1, which further comprises:

in the covering step, including a bottommost layer in the second layer sequence composed of an oxidizable material; and

oxidizing the bottommost layer of the second layer sequence at sidewalls of the second gate structures in the second area region.

9. The method according to claim 8, which further comprises removing the etch stop layer by an etching that etches the etch stop layer selectively with respect to the oxidized material of the bottommost layer of the first layer sequence on the sidewalls of the first gate structures and with respect to the oxidized material of the bottommost layer of the second layer sequence on the sidewalls of the second gate structures.

10. The method according to claim 1, which further comprises implanting an n-type doping into the second gate structures in a first partial region of the second area region.

11. The method according to claim 1, which further comprises implanting a p-type doping into the second gate structures in a second partial region of the second area region.

12. The method according to claim 1, which further comprises, in the depositing step, depositing a doped material as the bottommost layer of the first layer sequence.

13. The method according to claim 12, using an n-doped material as the doped material.

14. The method according to claims 1, which further comprises depositing polysilicon as the bottommost layer of both the first and the second layer sequence.

15. The method according to claim 1, which further comprises fabricating selection transistors for memory cells in the first area region.

16. The method according to claim 15, which further comprises producing the selection transistors in transistor pairs with a source/drain electrode implantation common to both transistors in the first area region.

17. The method according to claim 16, which further comprises:

providing a contact hole filling extending to sidewall coverings of the gate structures of both of the transistors of at least one of the transistor pairs; and

contact-connecting the common source/drain electrode implantation is contact-connected by the contact hole filling.

18. The method according to claims 2, which further comprises, in the depositing step, depositing the first layer sequence onto the semiconductor substrate covered with the gate oxide layer.