Method and apparatus for generating a data pattern for simultaneously testing multiple bus widths

• US 20030115009A1
• Filed: 12/14/2001
• Published: 06/19/2003
• Est. Priority Date: 12/14/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Ho, Stephen
• Granted Patent: US 6,704,677 B2
• Time in Patent Office: Days
• US Class Current: 702/119
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

One embodiment of the present invention provides a system that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths. The system first receives a list of bus widths to be tested. Next, the system receives a root test pattern with a width equal to the width of the smallest bus in the list. The system then inverts each bit of the root test pattern and concatenates this inverted pattern with the original pattern. Next, the system creates an additional pattern by repeating the second pattern sufficient times so that the width of this additional test pattern equals the width of the next larger bus. The system then creates a test pattern for the next larger bus by inverting each bit of the additional test pattern and concatenating this inverted test pattern with the additional test pattern.

Claims

1. A method that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths, the method comprising:

receiving a list of bus widths to be tested;

receiving a root test pattern, wherein a width of the root test pattern equals a smallest bus width in the list of bus widths;

creating a second test pattern by inverting each bit of the root test pattern and concatenating this inverted root pattern with the root test pattern;

creating a third test pattern by repeating the second test pattern zero or more times so that third test pattern width equals a next larger bus width in the list of bus widths; and

creating a fourth test pattern by inverting each bit of the third test pattern and concatenating this inverted third test pattern with the third test pattern;

whereby the fourth test pattern can be used to simultaneously test the smallest bus width and the next larger bus width in the list of bus widths.

2. The method of claim 1, further comprising:

while a larger bus width remains in the list of bus widths, repeating the steps of;

creating a first additional test pattern by repeating an immediately previous test pattern zero or more times so that a first additional test pattern width equals the next larger bus width in the list of bus widths; and

creating a second additional test pattern by inverting each bit of the first additional test pattern and concatenating this inverted first additional test pattern with the first additional test pattern.

3. The method of claim 2, further comprising transmitting a final test pattern created by this process through a set of buses related to the list of bus widths.

4. The method of claim 2, further comprising using a final test pattern created by this process to test a set of buses related to the list of bus widths.

5. The method of claim 2, wherein a final test pattern created by this process provides maximum transitional stress to each data bus.

6. The method of claim 2, wherein if the list of bus widths is not available the method further comprises:

creating a default list of bus widths; and

using the default list of bus widths as the list of bus widths to be tested.

7. The method of claim 6, wherein creating the default list of bus widths involves:

assuming one bit as the smallest bus width; and

assigning additional bus widths as increasing powers-of-two until a specified largest bus width is reached.

8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths, the method comprising:

receiving a list of bus widths to be tested;

receiving a root test pattern, wherein a width of the root test pattern equals a smallest bus width in the list of bus widths;

creating a second test pattern by inverting each bit of the root test pattern and concatenating this inverted root pattern with the root test pattern;

creating a third test pattern by repeating the second test pattern zero or more times so that third test pattern width equals a next larger bus width in the list of bus widths; and

creating a fourth test pattern by inverting each bit of the third test pattern and concatenating this inverted third test pattern with the third test pattern;

whereby the fourth test pattern can be used to simultaneously test the smallest bus width and the next larger bus width in the list of bus widths.

9. The computer-readable storage medium of claim 8, the method further comprising:

while a larger bus width remains in the list of bus widths, repeating the steps of;

creating a first additional test pattern by repeating an immediately previous test pattern zero or more times so that a first additional test pattern width equals the next larger bus width in the list of bus widths; and

creating a second additional test pattern by inverting each bit of the first additional test pattern and concatenating this inverted first additional test pattern with the first additional test pattern.

10. The computer-readable storage medium of claim 9, the method further comprising transmitting a final test pattern created by this process through a set of buses related to the list of bus widths.

11. The computer-readable storage medium of claim 9, the method further comprising using a final test pattern created by this process to test a set of buses related to the list of bus widths.

12. The computer-readable storage medium of claim 9, wherein a final test pattern created by this process provides maximum transitional stress to each data bus.

13. The computer-readable storage medium of claim 9, wherein if the list of bus widths is not available the method further comprises:

creating a default list of bus widths; and

using the default list of bus widths as the list of bus widths to be tested.

14. The computer-readable storage medium of claim 13, wherein creating the default list of bus widths involves:

assuming one bit as the smallest bus width; and

assigning additional bus widths as increasing powers-of-two until a specified largest bus width is reached.

15. An apparatus that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths, the apparatus comprising:

a receiving mechanism that is configured to receive a list of bus widths to be tested;

wherein the receiving mechanism is further configured to receive a root test pattern, and wherein a width of the root test pattern equals a smallest bus width in the list of bus widths;

a pattern creating mechanism that is configured to create a second test pattern by inverting each bit of the root test pattern and concatenating this inverted root pattern with the root test pattern;

wherein the pattern creating mechanism is further configured to create a third test pattern by repeating the second test pattern zero or more times so that third test pattern width equals a next larger bus width in the list of bus widths; and

wherein the pattern creating mechanism is further configured to create a fourth test pattern by inverting each bit of the third test pattern and concatenating this inverted third test pattern with the third test pattern;

whereby the fourth test pattern can be used to simultaneously test the smallest bus width and the next larger bus width in the list of bus widths.

16. The apparatus of claim 15:

wherein the pattern creating mechanism is further configured to create a first additional test pattern by repeating an immediately previous test pattern zero or more times so that a first additional test pattern width equals the next larger bus width in the list of bus widths; and

wherein the pattern creating mechanism is further configured to create a second additional test pattern by inverting each bit of the first additional test pattern and concatenating this inverted first additional test pattern with the first additional test pattern.

17. The apparatus of claim 16, further comprising a transmitting mechanism that is configured to transmit a final test pattern created by this process through a set of buses related to the list of bus widths.

18. The apparatus of claim 16, further comprising a testing mechanism that is configured to use a final test pattern created by this process to test a set of buses related to the list of bus widths.

19. The apparatus of claim 16, wherein a final test pattern created by this process provides maximum transitional stress to each data bus.

20. The apparatus of claim 16, further comprising:

a default creating mechanism that is configured to create a default list of bus widths; and

a testing mechanism that is configured to use the default list of bus widths as the list of bus widths to be tested.

21. The apparatus of claim 20, wherein the default creating mechanism further comprises:

a selecting mechanism that is configured to assume one bit as the smallest bus width; and

wherein the selecting mechanism is further configured to assign additional bus widths as increasing powers-of-two until a specified largest bus width is reached.