Time slot protocol

• US 20030115369A1
• Filed: 03/26/2002
• Published: 06/19/2003
• Est. Priority Date: 12/14/2001
• Status: Active Grant

• Current Assignee: Smiths Aerospace, Inc. (Smiths Group International Holdings Ltd.)
• Original Assignee: Smiths Aerospace, Inc. (Smiths Group International Holdings Ltd.)
• Inventors: Vanbaran, Gerald W., Walter, Randy L., Hodges, Donald G., Albers, Courtney L., Schroeder, John L.
• Granted Patent: US 7,486,693 B2
• Time in Patent Office: Days
• US Class Current: 709/253
• CPC Class Codes: H04L 12/4035 in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64
• CPC Class Codes: H04L 2012/4028 the transportation system being an aircraft
• CPC Class Codes: H04L 69/28 Timers or timing mechanisms used in protocols

Abstract

A computing network uses Time Division Multiplexing (TDM) to divide the time on a bus into a plurality of frames, each frame having a plurality of time slots. Each time slot is assigned no more than one of the plurality of devices within a collision domain, the assignments indicating the identity of the device permitted to transmit packets onto the network during the assigned time slot. A bus cadence unit simultaneously sends an epoch packet initiating the frame. The epoch packet contains a time slot assignment table containing the time slot assignments, the device identification, as well as a time slot offset and duration. Each device on the network is configured to measure a frame interval between repeating epoch packets. The measured frame interval is further processed in each receiving node to obtain a calibrated frame interval. The calibrated frame interval is used to accurately synchronize transmissions of data from the various devices onto the network. A time slot protocol governor in each node controls access to the bus to only the assigned time slot or slots using the calibrated frame interval to reduce or eliminate synchronization errors.

Claims

1. A method of operating a network having a plurality of devices coupled to a shared bus comprising the step of transmitting an epoch packet indicating the beginning of a frame wherein the frame has a plurality of time slots and wherein the epoch packet includes assignments of the time slots to the devices, and time slot offset and time slot duration information for each time slot assignment.

2. The method of claim 1 further including the step of determining a transmission time, in each device, using information in the epoch packet.

3. The method of claim 2 further comprising the step of controlling access to the shared bus during one of a plurality of time slots in a frame using a frequency calibration parameter, configured to adjust at least one transmission timer, calculated using measured frame intervals.

4. The method of claim 1 further comprising the steps of:

assigning to each time slot no more than one of the plurality of devices within a collision domain, wherein said assignments indicate the identity of the device permitted to transmit packets onto the shared bus of the network during the assigned time slot;

defining a table that includes said time slot assignments, said table further including time slot offset and slot duration data for each time slot;

simultaneously sending the table over the shared bus of the network to each of the plurality of devices in said epoch packet.

5. The method of claim 3 wherein said frequency calibration parameter comprises a calibration ratio, said controlling step includes the substep of:

determining the calibration ratio using a weighted average of the measured frame intervals and a preselected frame interval;

generating a calibrated time slot offset using said calibration ratio and said time slot offset from said table for one of the plurality of time slots; and

generating a calibrated slot duration using said calibration ratio and said slot duration from said table for said one of the plurality of time slots.

6. The method of claim 5 further comprising the step of:

transmitting packets onto the shared bus of the network during said one time slot in accordance with said calibrated time slot offset, and said calibrated slot duration.

7. The method of claim 6 wherein said step of transmitting is Ethernet compliant.

8. The method of claim 6 wherein said transmitting step includes the substep of:

restricting transmission of packets by the device associated with said one time slot using hardware gating logic.

9. The method of claim 6 wherein said controlling step is performed with respect to each device on said network during respectively associated time slots.

10. An adapter for allowing a device to access a shared bus of a network for transmitting packets during one or more time slots selected from a plurality of time slots defining a frame, said one or more time slots being assigned to said device, said adapter comprising:

a physical interface device (PHY) unit configured to receive incoming packets from the bus, said PHY being further configured to output outgoing packets;

a media access control (MAC) unit;

a governor coupled to said physical interface device and said MAC;

a protocol unit configured to process an epoch packet during each frame, receipt by the device of said epoch packet indicating the beginning of each frame, said epoch packet having a table including (i) time slot assignments for devices on the bus, (ii) a time slot offset for each time slot assignment, and (iii) a time slot duration for each time slot assignment; and

wherein said governor is configured to control transmission of said outgoing packets onto said bus during said assigned one or more time slots in accordance with said time slot offset and duration data.

11. The adapter of claim 10 wherein said network includes a bus cadence unit (BCU) configured to transmit the epoch packets.

12. The adapter of claim 10 wherein said governor includes means for timestamping each received packet.

13. The adapter of claim 12 wherein said PHY is Ethernet compliant.

14. The adapter of claim 10 wherein said timestamping means includes a programmable timer.

15. The adapter of claim 11 wherein said protocol unit includes means for measuring frame intervals using respective timestamps of consecutive epoch packets.

16. The adapter of claim 15 wherein said protocol unit further includes means for computing a weighted average epoch-packet frame interval based on a plurality of measured frame intervals.

17. The adapter of claim 16 wherein said governor is configured to control access to said bus using a frequency calibration parameter configured to adjust a transmission timer.

18. The adapter of claim 17 wherein said calibration parameter comprises a calibration ratio, said protocol unit further includes means for determining said calibration ratio based on said weighted average epoch packet frame interval and a predetermined frame interval.

19. The adapter of claim 18 wherein said protocol unit further includes means for calculating (i) a calibrated time slot offset using said calibration ratio and a slot offset selected from said table;

and (ii) a calibrated time slot duration using said calibration ratio and a slot duration selected from said table.

20. The adapter of claim 19 wherein said governor includes means for controlling transmission of packets onto said bus during said assigned one or more time slots responsive to said calibrated time slot offset and said calibrated time slot duration.

21. The adapter of claim 20 wherein governor includes a gate for passing said outgoing packets to said PHY onto said bus only during said assigned one or more time slots, as determined, said calibrated slot offset and said calibrated slot duration, to thereby enforce strict deterministic access to said bus.

22. The adapter of claim 21 where said controlling means includes (i) a slot timer configured to be loaded with said calibrated slot duration and (ii) an offset timer adapted to be configured with said calibrated slot offset.

23. An adapter for allowing a device to access a shared bus of a network for transmitting packets during one or more timeslots selected from a plurality of time slots defining a frame, said one or more time slots being assigned to said device for transmission, said adapter comprising:

a physical interface device (PHY) unit configured to receive incoming packets from the bus, said PHY being further configured to output outgoing packets;

a media access control (MAC) unit;

a governor coupled to said physical interface device and said MAC;

a protocol unit configured to generate a transmission protection envelope signal based on data contained in epoch packets received at the beginning of each frame; and

wherein said governor further includes a pass gate configured to selectively prevent transmission of said outgoing packets onto the bus outside of said assigned one or more time slots in accordance with said transmission protection envelope signal.

24. The adapter of claim 23 wherein said PHY is Ethernet compliant.

25. An adapter for allowing a device to access a shared bus of a network for transmitting packets during one or more time slots selected from a plurality of time slots defining a frame, said one or more time slots being assigned to said device, said network including a bus cadence unit (BCU) configured to transmit an epoch packet during said frame, said epoch packet comprising timing information and at least one reference bus attribute, said adapter comprising:

a media access control (MAC) unit configured to receive incoming packets from the bus via a physical interface device (PHY), said MAC being further configured to output outgoing packets destined for said bus; and

a protocol unit coupled to said MAC and configured to process said incoming packets and generate at least one measured bus attribute corresponding to said reference bus attribute, said protocol unit being further configured to generate a message indicative of a condition of said bus based on said reference bus attribute and said measured bus attribute.

26. The adapter of claim 25 wherein said reference bus attribute is selected from the group comprising an epoch packet timeout attribute, a frame rate attribute, a frequency tolerance attribute, a jitter tolerance and a filter attribute.

27. The adapter of claim 26 wherein said incoming packets being processed by said protocol unit to generate said measured bus attribute from said epoch packets.

28. The adapter of claim 25 wherein said MAC is Ethernet compliant.