Method and apparatus for selectively compacting test responses

• US 20030115521A1
• Filed: 01/29/2003
• Published: 06/19/2003
• Est. Priority Date: 11/23/1999
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Granted Patent: US 6,829,740 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

Claims

1. An apparatus used in testing of an integrated circuit, comprising:

a circuit under test that is part of the integrated circuit;

at least one spatial compactor to compress test responses from the circuit under test; and

a selector circuit coupled between the circuit under test and the spatial compactor that masks one or more of the test responses that are received from the circuit under test.

2. The apparatus of claim 1, wherein the spatial compactor includes a feedback-free network of combinational logic.

3. The apparatus of claim 1, wherein the selector circuit includes a register coupled to one or more AND gates.

4. The apparatus of claim 1, wherein the selector circuit includes a register that stores a flag that when activated allows all the test responses pass to the compactor and that when deactivated allows none of the test responses pass to the compactor.

5. The apparatus of claim 1, further including scan chains within the circuit under test.

6. The apparatus of claim 5, wherein each scan chain has an output and the selector circuit includes a set of logic gates having first inputs coupled to the outputs of the scan chains and second inputs coupled to a register.

7. The apparatus of claim 1 wherein the compactor and selector circuit are physically located on the integrated circuit.

8. The apparatus of claim 1 wherein the compactor and selector circuit are physically located externally of the integrated circuit.

9. The apparatus of claim 1 wherein masking a test response includes masking one or more bits of a test response in a scan chain.

10. The apparatus of claim 1, further including automatic testing equipment (ATE) coupled to the integrated circuit, the ATE being external to the integrated circuit and controlling the selector circuit.

11. The apparatus of claim 1, wherein the spatial compactor includes only linear logic gates.

12. A method for selectively compacting test responses of a circuit under test, comprising:

receiving N test responses from scan chains in the circuit under test;

selectively preventing between 0 and N of the test responses from being passed to a spatial compactor while allowing the remaining test responses to be passed to the spatial compactor; and

spatially compacting the test responses passed to the spatial compactor.

13. The method of claim 12, further including shifting each test response serially to the spatial compactor.

14. The method of claim 12 further including:

loading the scan chains with predetermined test patterns for testing the circuit under test;

and

generating and storing test responses in response to applying the test patterns to the circuit under test.

15. The method of claim 12, wherein selectively preventing includes controlling which test responses are passed to the spatial compactor by using external automatic testing equipment.

16. The method of claim 12, further including:

loading the scan chains with predetermined test patterns;

storing test responses in the scan chains;

identifying one scan chain as a scan chain of interest and passing only the test response within the identified scan chain to the compactor while preventing all other test responses from being passed to the compactor.

17. The method of claim 12 wherein selectively preventing the test responses from being passed to the spatial compactor includes preventing one or more bits of a test response from being passed to the compactor while allowing other bits of the test response to pass to the compactor.

18. An apparatus used in testing of integrated circuits, comprising:

scan chains within the integrated circuit;

a selector circuit coupled to the scan chains; and

a spatial compactor coupled to the selector circuit.

19. The apparatus of claim 18, wherein the spatial compactor includes a feedback-free network of linear gates.

20. The apparatus of claim 18, further including automatic testing equipment coupled to the integrated circuit.

21. The apparatus of claim 18, wherein the selector circuit is directly connected between the spatial compactor and the scan chains, without intervening logic.