Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices

• US 20030116439A1
• Filed: 12/21/2001
• Published: 06/26/2003
• Est. Priority Date: 12/21/2001
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Seo, Soon-Chen, Chen, Zheng, Edelstein, Daniel C., Chen, Xiaomeng, McGahay, Vincent, Sambucetti, Carlos J.
• Application Number:
  US10/026,176
• Publication Number:
  US 20030116439A1
• Time in Patent Office: Days
• US Class Current: 205/125
• CPC Class Codes: C23C 18/1605 by masking
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H05K 3/4647 by applying an insulating layer around previously made via studs

Abstract

An advanced back-end-of-line (BEOL) integration scheme for semiconductor devices using very low-k dielectric materials is disclosed. The disclosed method for forming a metal interconnect structure in a semiconductor integrated circuit device comprises forming the metal interconnects using a through-mask plating (TMP) process, and encapsulating the interconnects with a barrier layer by selectively depositing a barrier layer material using an electroless liner plating process or by non-selectively depositing a blanket insulator diffusion barrier layer using PVD or CVD techniques.

Claims

1. A method for forming a metal interconnect in an integrated circuit device, the method comprising the steps of:

(a) depositing a metal seed layer onto a partially fabricated integrated circuit device;

(b) depositing a photoresist layer onto the metal seed layer;

(c) forming an opening in the photoresist layer by a photolithography process, thereby exposing a portion of the metal seed layer;

(d) depositing metal in the opening by a plating process;

(e) removing the photoresist layer and metal seed layer, thereby exposing the partially fabricated integrated circuit device;

(f) depositing a conformal barrier layer onto the metal; and

(g) depositing a dielectric material onto the partially fabricated integrated circuit device.

2. The method of claim 1, wherein the metal seed layer is formed of a material to which the metal is directly plated.

3. The method of claim 1, wherein the metal seed layer is copper.

4. The method of claim 1, wherein the metal is deposited by an electrolytic plating process.

5. The method of claim 1, wherein the metal is deposited by an electroless plating process.

6. The method of claim 1, wherein the metal is copper, and the copper is deposited by an electrolytic plating process comprising the steps of:

immersing the partially fabricated integrated circuit device into a plating bath comprising a dissolved cupric salt; and

applying electric current to the metal seed layer.

7. The method of claim 1, wherein the barrier layer is selectively deposited onto the metal by an electroless plating process.

8. The method of claim 7, wherein the electroless plating process comprises the steps of:

depositing catalytic particles onto the surface of the metal; and

immersing the partially fabricated integrated circuit device into a plating bath.

9. The method of claim 8, wherein the metal is copper;

the catalytic particles are selected from a group consisting of palladium, cobalt and nickel; and

the plating bath comprises a hypophosphite reducing agent.

10. The method of claim 1, wherein the barrier layer is selected from a group consisting of CoWP, CoP, NiP, NiWP, CoB, NiB and CoWB.

11. The method of claim 1, wherein the barrier layer is formed of an insulator material.

12. The method of claim 1, wherein the barrier layer is deposited by a chemical vapor deposition process or physical vapor deposition process.

13. The method of claim 1, wherein the barrier layer comprises a first layer of material selected from the group consisting of CoWP, CoP, NiP, NiWP, CoB, NiB and CoWB, and a second layer of insulator material.

14. The method of claim 1, wherein the dielectric material is deposited by a chemical vapor deposition process, a physical vapor deposition process, or a spin-coating process.

15. The method of claim 1, wherein the dielectric material has a dielectric constant of less than about 3.0.

16. The method of claim 1, wherein the dielectric material comprises an organic polymer material, and is deposited by spin-coating the dielectric material onto the partially fabricated integrated circuit device.

17. The method of claim 1, wherein the dielectric material comprises a carbon-doped silicate glass, and is deposited by a plasma-enhanced chemical vapor deposition process.

18. The method of claim 1, further comprising the step of:

(h) removing excess dielectric material and the top portion of the barrier layer, thereby exposing the top surface of the metal.

19. The method of claim 1, further comprising repeating steps (c) through (e), prior to performing step (f).

20. The method of claim 1, further comprising, prior to step (a), the step of:

depositing a conductive barrier liner onto the partially fabricated integrated circuit device.