Semiconductor chip and semiconductor device using the semiconductor chip

• US 20030116790A1
• Filed: 12/19/2002
• Published: 06/26/2003
• Est. Priority Date: 06/21/2000
• Status: Active Grant

• Current Assignee: Kyushu Hitachi Maxell Ltd. (Maxell, Ltd.)
• Original Assignee: Hitachi Maxell Limited (Hitachi, Ltd.)
• Inventors: Hino, Yoshiharu, Kishimoto, Kiyoharu, Kikuchi, Yuji, Nakagawa, Kazunari
• Granted Patent: US 6,838,773 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07756 the connection being non-galvanic, e.g. capacitive
• CPC Class Codes: G06K 19/07775 the antenna being on-chip
• CPC Class Codes: G06K 19/07779 the inductive antenna being a coil
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A semiconductor chip of rewiring layer-integral type capable of preventing a maloperation by noise and a deterioration of communication characteristics and a semiconductor device with excellent communication characteristics; the semiconductor chip, wherein a rewiring layer (3) is formed on a circuit formed surface (1a) through an insulating layer (2) so as to form an antenna coil (4) with the rewiring layer (3), the antenna coil (4) is formed around the periphery of an analog circuit (21) on the circuit formed surface (1a) by avoiding forming on the analog circuit (21), the analog circuit (21) may be formed by collecting analog circuits to be formed in the semiconductor chip (1A) therein, may be one of the particularly noise-susceptible analog circuits such as a power circuit, a calculation amplifier, a comparison amplifier, an RF receiving part, an RF transmitting part, an RF synthesizer part, and a voltage build-up circuit and an amplifying circuit forming a part of a memory part, or may be a coil provided in a part of the analog circuit formed in the semiconductor chip (1A).

Claims

1. A semiconductor chip having a rewiring layer formed on a circuit-formed surface through an insulating layer in such a manner as to be integral with said chip, wherein all of or a part of an analog circuit formed on said circuit-formed surface and said rewiring layer are arranged not to overlap each other through said insulating layer.

4. A semiconductor chip according to any of claims 1-3, wherein an antenna coil, connected at each end to an input/output terminal formed on said circuit-formed surface, for non-contact communication is formed from said rewiring layer.

5. A semiconductor chip according to any of claims 1-3, wherein bump-setting wires are formed from said rewiring layer, and wherein said bump-setting wires are connected at one end to input/output terminals formed on said circuit-formed surface and have bumps formed at the other end thereof.

6. A semiconductor chip according to any of claims 1-5, wherein said circuits formed on said circuit-formed surface constitute a radio transmission circuit formed by CMOS technology.

7. A semiconductor chip according to any of claims 1-6, wherein said circuits formed on said circuit-formed surface constitute a radio transmission circuit for transmitting, receiving or exchanging signals of frequencies of 800 MHz or higher with an external device.

2. A semiconductor chip having a rewiring layer formed on a circuit-formed surface through an insulating layer in such a manner as to be integral with said chip, wherein said rewiring layer and at lest one of a power circuit, an operational amplifier, a comparison amplifier, an RF receiving part, an RF transmitting part, and an RF synthesizer formed on said circuit-formed surface are arranged so as not to overlap each other through said insulating layer.

3. A semiconductor chip having a rewiring layer formed on a circuit-formed surface through an insulating layer in such a manner as to be integral with said chip, wherein a coil formed on said circuit-formed surface and said rewiring layer are arranged so as not to overlap each other through said insulating layer.

8. A semiconductor device having a semiconductor chip mounted on a substrate of predetermined dimensions and shape, wherein said semiconductor chip has a rewiring layer formed on a circuit-formed surface through an insulating layer in such a manner as to be integral with the chip, and wherein said rewiring layer and all or a part of an analog circuit formed on the circuit-formed surface are arranged not to overlap each other through said insulating layer.

9. A semiconductor device having a semiconductor chip mounted on a substrate of predetermined dimensions and shape, wherein said semiconductor chip has a rewiring layer formed on a circuit-formed surface through an insulating layer in such a manner as to be integral with the chip, and wherein said rewiring layer and at least one of a power circuit, an operational amplifier, a comparison amplifier, an RF receiving part, an RF transmitting part, and an RF synthesizer, formed on said circuit-formed surface, are arranged not to overlap each other through the insulating layer.

10. A semiconductor device having a semiconductor chip mounted on a substrate of predetermined dimensions and size, wherein in said semiconductor chip, a rewiring layer is formed on a circuit-formed surface through an insulating layer in such a manner as to be integral with said chip, and wherein a coil formed on said circuit-formed surface and said rewiring layer are arranged so as not to overlap each other through said insulating layer.