Clock generating circuit

• US 20030117204A1
• Filed: 01/23/2003
• Published: 06/26/2003
• Est. Priority Date: 09/19/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Morishita, Fukashi, Fujii, Nobuyuki, Yamazaki, Akira, Akiyama, Mihoko, Taito, Yasuhiko, Okamoto, Mako
• Granted Patent: US 6,781,431 B2
• Time in Patent Office: Days
• US Class Current: 327/291
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/70 time intervals between all adjacent pulses of one train being equal

Abstract

The clock generating circuit includes: an oscillator generating a reference clock signal; an EX-OR gate connected in a ring configuration; and first and second D latch circuits. The EX-OR gate inverts a clock signal to provide the inverted clock signal to the first D latch circuit when an activating signal is at H level. In this case, the clock signal is a clock signal having a clock cycle period of twice that of the reference clock signal. The EX-OR gate provides the clock signal direct to the first D latch circuit when the activating signal is set to L level. In this case, level transition of the clock signal is ceased. Hence, generation of a glitch in the clock signal is prevented from occurring.

Claims

1. A clock generating circuit generating a clock signal comprising:

an oscillator generating a reference clock signal;

a first latch circuit, provided between first and second nodes, transmitting a level on said first node to said second node when said reference clock signal is at a first logic level and holding a level on said second node in response to transition of said reference clock signal from said first logic level to a second logic level;

a second latch circuit, provided between said second node and an output node for outputting said clock signal, transmitting a level on said second node to said output node when said reference clock signal is at said second logic level and holding a level on said output node in response to transition of said reference clock signal from said second logic level to said first logic level; and

a logic circuit, provided between said output node and said first node, and providing a complementary level of a level on said output node to said first node to generate said clock signal when an activating signal is at a first level, while transmitting a level on said output node to said first node to cease generation of said clock signal when the activating signal is at a second level.

2. The clock generating circuit according to claim 1, further comprising:

a noise filter, provided between an output node of said logic circuit and said first node, and for eliminating noise from an output signal of said logic circuit to provide said output signal to said first node.

3. The clock generating circuit according to claim 1, wherein said oscillator is activated in response to transition of said activation signal to said first level, while being deactivated in response to transition thereof to said second level.

4. The clock generating circuit according to claim 3, further comprising:

a delay circuit delaying said activating signal by a prescribed time to provide said activating signal to said oscillator.

5. The clock generating circuit according to claim 1, wherein said clock signal is used as a driving clock signal for a charge pump circuit.

6. A clock generating circuit generating a clock signal comprising:

a ring oscillator including an odd number of first inverters connected in a ring configuration, being activated to generate a clock signal when an activating signal is at a first level, while being deactivated to cease generation of said clock signal when said activating signal is at a second level; and

a latch circuit, connected to an output node of said ring oscillator, and holding a level of an output node of said ring oscillator in response to transition of said activating signal from said first level to said second level.

7. The clock generating circuit according to claim 6, wherein one first inverter of said odd number of first inverters is a clocked inverter that is activated when said activating signal is at said first level, while being deactivated when said activating signal is at said second level, and whose output node serves as an output node of said ring oscillator.

8. The clock generating circuit according to claim 6, wherein said ring oscillator further includes:

a transfer gate inserted between an output node of one first inverter of said odd number of first inverters and an input node of the subsequent first inverter thereof, and being conductive when said activating signal is at said first level, while being nonconductive when said activating signal is at said second level, wherein said input node of said subsequent inverter serves as an output node of said ring oscillator.

9. The clock generating circuit according to claim 6, wherein a first inverter includes:

first and second transistors of respective different conductivity types connected in series between first and second power source potential lines; and

at least one constant current source connected in series to said first and second transistors between said first and second power source potential lines.

10. The clock generating circuit according to claim 6, wherein said latch circuit further comprising:

a second inverter connected between an output node of said ring oscillator and an output node of said clock generating circuit; and

a clocked inverter, in inverse parallel connection to said second inverter, being deactivated when said activating signal is at said first level, while being activated when said activating signal is at said second level.

11. The clock generating circuit according to claim 10, further comprising:

at least three of said second inverter, which are connected in series between an output node of said ring oscillator and an output node of said clock generating circuit.

12. The clock generating circuit according to claim 10, further comprising:

a noise filter inserted between an output node of said second inverter and an output node of said clock generating circuit, and for eliminating noise from an output signal of said second inverter.

13. The clock generating circuit according to claim 6, wherein said clock signal is used as a driving clock signal for a charge pump circuit.