Command packet system and method supporting improved trick mode performance in video decoding systems

• US 20030118116A1
• Filed: 12/11/2002
• Published: 06/26/2003
• Est. Priority Date: 09/12/2001
• Status: Active Grant

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Erickson, David, Aggarwal, Gaurav, Kellerman, Marcus, Hulmani, Girish, Demas, Jason, Rao, Arun Gopalakrishna, Bhatia, Sandeep
• Granted Patent: US 7,149,248 B2
• Time in Patent Office: Days
• US Class Current: 375/240.25
• CPC Class Codes: G06T 9/004 Predictors, e.g. intraframe, interframe coding
• CPC Class Codes: H04N 19/107 between spatial and temporal predictive coding, e.g. picture refresh
• CPC Class Codes: H04N 19/159 Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/4147 PVR [Personal Video Recorder] H04N5/76 takes precedence ; arrangements for broadcast with accumulation-type receivers H04H20/40
• CPC Class Codes: H04N 21/42623 involving specific decryption arrangements
• CPC Class Codes: H04N 21/42661 for reading from or writing on a magnetic storage medium, e.g. hard disk drive
• CPC Class Codes: H04N 21/4334 Recording operations recording of a television signal H04N5/76; arrangements for recording or accumulating broadcast information or broadcast-related information H04H60/27
• CPC Class Codes: H04N 21/4348 Demultiplexing of additional data and video streams
• CPC Class Codes: H04N 21/4385 Multiplex stream processing, e.g. multiplex stream decrypting
• CPC Class Codes: H04N 21/4402 involving reformatting operations of video signals for household redistribution, storage or real-time display details of conversion of video standards at pixel level H04N7/01; video transcoding H04N19/40; adapting incoming signals to the display format of the display terminal G09G5/005; media handling at the source in data packet switching networks H04L65/764
• CPC Class Codes: H04N 21/6587 Control parameters, e.g. trick play commands, viewpoint selection
• CPC Class Codes: H04N 21/8455 involving pointers to the content, e.g. pointers to the I-frames of the video stream
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 5/781 on disks or drums
• CPC Class Codes: H04N 5/83 on disks or drums
• CPC Class Codes: H04N 9/8042 involving data reduction
• CPC Class Codes: H04N 9/8063 using time division multiplex of the PCM audio and PCM video signals

Abstract

A system, method, and apparatus for reducing the video decoder processing requirements are presented herein. During a rewind operation, a reference picture for a group of pictures is decoded and stored into a reference frame buffer. By storing a reference picture for the group, the reference picture need not be decoded to display each picture in the group during the rewind operation.

Claims

1. A method for decoding pictures, said method comprising:

storing a reference picture;

decoding a first prediction picture from the reference picture;

decoding a second prediction picture from the reference picture;

decoding a display picture from the first prediction picture and the second prediction picture; and

providing the display picture to a display device.

2. The method of claim 1, wherein the reference picture is an intra-coded picture.

3. The method of claim 1, wherein the reference picture is a clean reference picture.

4. The method of claim 1, wherein the reference picture is a midpoint picture in an EP to EP segment.

5. The method of claim 1, further comprising:

storing the first prediction picture; and

storing the second prediction picture.

6. A decoder system for decoding pictures, said method comprising:

a first frame buffer for storing a reference picture;

a second frame buffer for storing a first prediction picture;

a third frame buffer for storing a second prediction picture; and

a processor for decoding a display picture from the first prediction picture and the second prediction picture.

7. The decoder of claim 6, wherein the reference picture is an intra-coded picture.

8. The decoder of claim 6, wherein the reference picture is a clean reference picture.

9. The decoder of claim 6, further comprising a fourth frame buffer for storing a midpoint picture.

10. The decoder of claim 6, further comprising a fourth frame buffer for storing the display picture.

11. An integrated circuit comprising:

memory for storing a plurality of instructions;

a processor connected to the memory;

wherein execution of the plurality of instructions by the processor causes;

storing a reference picture;

decoding a first prediction picture from the reference picture;

decoding a second prediction picture from the reference picture;

decoding a display picture from the first prediction picture and the second prediction picture; and

providing the display picture to a display device.

12. The integrated circuit of claim 11, wherein the reference picture is an intra-coded picture.

13. The integrated circuit of claim 11, wherein the reference picture is a clean reference picture.

14. The integrated circuit of claim 11, wherein the reference picture is a midpoint picture in an EP to EP stream.

15. The integrated circuit of claim 11, wherein executing the plurality of instructions by the processor further causes:

storing the first prediction picture; and

storing the second prediction picture.