Direct modulation architecture for amplitude and phase modulated signals in multi-mode signal transmission

• US 20030118143A1
• Filed: 04/30/2002
• Published: 06/26/2003
• Est. Priority Date: 12/26/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bellaouar, Abdellatif, Gore, Charles, Laster, Jeff D.
• Granted Patent: US 7,095,819 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04L 5/06 the signals being represented by different frequencies combined with time-division multiplexing H04L5/26

Abstract

Multiple-mode direct phase/amplitude modulation circuitry (20) for use in a transceiver (17) of a device such as a wireless handset (10) is disclosed. The modulation circuitry (20) includes a modulation loop (36) for modulating a phase signal into a Gaussian-Minimum-Shift-Keyed (GMSK) signal for transmission in a first mode. The modulation loop (36) may include a phase-locked loop (45) with its frequency controlled by a Σ-Δ demodulation of a compensated version of the phase signal, or alternatively may produce a modulated signal from a direct digital synthesis circuit (70; 70′). An amplitude signal is converted into an analog signal and applied to a single-sideband mixer (43) for combination with a frequency multiplied version of the phase-modulated signal (GMSK(t); PH(t)), producing an amplitude and phase modulated signal for transmission in a second mode.

Claims

1. A multiple-mode amplitude and phase direct modulator circuit, comprising:

a phase modulator leg, comprising;

compensation circuitry for applying delay compensation to an input phase signal;

a modulation loop, for receiving the compensated input phase signal and for producing a phase-modulated output signal as a first mode output signal; and

a frequency multiplier, coupled to the modulation loop, for multiplying the frequency of the phase-modulated output signal;

an amplitude modulator leg, comprising;

a digital-to-analog converter, for converting an input amplitude digital sequence to an analog amplitude modulated signal; and

a mixer, having a first input coupled to the frequency multiplier to receive the phase-modulated output signal, having a second input coupled to the digital-to-analog converter to receive the analog amplitude-modulated signal, the mixer for combining the multiplied phase-modulated output signal and the analog amplitude-modulated signal into a second mode output signal.

2. The circuit of claim 1, further comprising:

a filter circuit, coupled between the digital-to-analog converter and the second input of the mixer.

3. The circuit of claim 1, wherein the modulation loop comprises a phase-locked loop, the phase-locked loop including a low-pass loop filter;

and further comprising;

a modulation compensation circuit, coupled to the compensation circuitry and to the modulation loop, for compensating the effects of the loop filter.

4. The circuit of claim 3, wherein the phase-locked loop further comprises:

a phase detector, for comparing a feedback signal to a reference signal, the phase detector having an output coupled to the low-pass loop filter;

a voltage-controlled oscillator, having a control input coupled to the low-pass loop filter, for generating the phase-modulated signal at an output; and

a frequency divider, having an input coupled to the output of the voltage-controlled oscillator, for generating the feedback signal;

wherein the modulation loop further comprises;

a Σ

-Δ

modulator, having an input coupled to receive a sum of a channel frequency and the compensated input phase signal, and having an output coupled to a control input of the frequency divider;

and wherein the modulation compensation circuit comprises;

a phase demodulator, for demodulating the phase-modulated signal; and

a comparator for comparing the demodulated phase-modulated signal to a signal based on the input phase signal, and for producing an error signal coupled to the input of the Σ

-Δ

modulator.

5. The circuit of claim 1, wherein the compensation loop comprises:

a direct digital frequency synthesis circuit, receiving the compensated input phase signal and a channel frequency at respective inputs, and for generating an analog signal corresponding to a phase-modulation of the channel frequency;

a phase-locked-loop circuit, having an input for receiving the analog signal from the direct digital frequency synthesis circuit, and for producing a phase-modulated signal at an output.

6. The circuit of claim 5, wherein the direct digital frequency synthesis circuit comprises:

phase accumulator circuitry, for periodically combining a digital channel frequency word and a digital signal based on the input phase signal to produce a digital phase accumulator output sequence;

a memory for producing a sine wave output sequence responsive to the phase accumulator output;

a digital-to-analog converter, for converting the sine wave output sequence into an analog signal.

7. The circuit of claim 5, wherein the direct digital frequency synthesis circuit comprises:

an accumulator for periodically accumulating a channel frequency word, the accumulator having an output corresponding to a most significant bit of the accumulator contents; and

edge correction and noise shaping circuitry, having an input receiving a sequence of the most significant bit of the accumulator contents, for adjusting the spacing of bit values in the sequence to produce an output sequence coupled to the phase-locked loop circuit.

8. The circuit of claim 7, wherein the most significant bit of the accumulator contents corresponds to a carry bit.

9. The circuit of claim 1, wherein the phase-modulated signal is a Gaussian-Minimum-Shift-Keyed modulated signal..

10. A method of producing multiple-mode modulated signals, comprising the steps of:

receiving an input phase signal and an input amplitude signal, each corresponding to a sequence of digital words;

modulating the input phase signal to produce an analog phase-modulated output signal;

multiplying the frequency of a signal based on the phase-modulated signal to produce a multiplied phase-modulated signal;

converting the input amplitude signal to an analog amplitude signal; and

mixing the analog amplitude signal and the multiplied phase-modulated signal to produce an amplitude and phase modulated output signal.

11. The method of claim 10, wherein the modulating step comprises:

adding the input phase signal to a channel frequency signal;

modulating the added input phase signal and channel frequency signal using a Σ

-Δ

modulator, to produce a modulated output; and

applying the modulated output to a frequency divider in a phase-locked-loop;

wherein the output of the phase-locked loop presents the analog-phase-modulated output signal.

12. The method of claim 11, further comprising:

phase-demodulating the analog phase-modulated signal;

comparing the phase-demodulated analog phase-modulated signal to a delayed version of the input phase signal to produce an error signal;

adding the error signal to the input phase signal so that the adding step adds the sum of the input phase signal and the error signal to the channel frequency signal.

13. The method of claim 10, wherein the modulating step comprises:

synthesizing a direct digital frequency from the input phase signal and a channel frequency signal;

converting the direct digital frequency to an analog synthesized signal;

applying the analog synthesized signal to a phase-locked loop to produce the analog phase-modulated signal.

14. The method of claim 10, wherein the synthesizing step comprises:

periodically adding the input phase signal to an accumulation of the channel frequency signal;

applying the result of the adding step to a sine wave table to produce a digital sine wave value.

15. The method of claim 10, wherein the synthesizing step comprises:

periodically accumulating a digital word corresponding to the channel frequency signal, to produce a bit sequence of a most significant bit of the accumulation; and

correcting the bit sequence to more uniformly space bit values in the bit sequence.

16. The method of claim 10, wherein the phase-modulated output signal is a Gaussian-Minimum-Shift-Keyed modulated signal..

17. A wireless telephone device, comprising:

a microphone;

a speaker;

baseband circuitry, coupled to the microphone and speaker, to process audio signals received from and presented to the microphone and speaker, respectively;

quadrature phase modulator circuitry coupled to the baseband circuitry, for encoding signals from the baseband circuitry into phase and amplitude digital signals;

transceiver circuitry, comprising;

a phase modulator leg, comprising;

compensation circuitry for applying delay compensation to the phase digital signal;

a modulation loop, for receiving the compensated input phase signal and for producing a phase-modulated output signal as a first mode output signal; and

a frequency multiplier, coupled to the modulation loop, for multiplying the frequency of the phase-modulated output signal;

an amplitude modulator leg, comprising;

a digital-to-analog converter, for converting the amplitude digital signal to an analog amplitude modulated signal; and

a mixer, having a first input coupled to the frequency multiplier to receive the, having a second input coupled to the digital-to-analog converter to receive the analog amplitude-modulated signal, the mixer for combining the multiplied phase-modulated output signal and the analog amplitude-modulated signal into a second mode output signal; and

amplifier circuitry for amplifying the first mode output signal and the second mode output signal, for transmission via an antenna.

18. The device of claim 17, wherein the modulation loop comprises a phase-locked loop, the phase-locked loop including a low-pass loop filter;

and wherein the phase modulator leg of the transceiver circuitry further comprises;

a modulation compensation circuit, coupled to the compensation circuitry and to the modulation loop, for compensating the effects of the loop filter.

19. The device of claim 18, wherein the phase-locked loop further comprises:

a phase detector, for comparing a feedback signal to a reference signal, the phase detector having an output coupled to the low-pass loop filter;

a voltage-controlled oscillator, having a control input coupled to the low-pass loop filter, for generating the phase-modulated signal at an output; and

a frequency divider, having an input coupled to the output of the voltage-controlled oscillator, for generating the feedback signal;

wherein the modulation loop further comprises;

a Σ

-Δ

modulator, having an input coupled to receive a sum of a channel frequency and the compensated phase digital signal, and having an output coupled to a control input of the frequency divider;

and wherein the modulation compensation circuit comprises;

a phase demodulator, for demodulating the phase-modulated signal; and

a comparator for comparing the demodulated phase-modulated signal to a signal based on the phase digital signal, and for producing an error signal coupled to the input of the Σ

-Δ

modulator.

20. The device of claim 18, wherein the compensation circuit comprises:

a direct digital frequency synthesis circuit, receiving the compensated phase digital signal and a channel frequency at respective inputs, and for generating an analog signal corresponding to a phase-modulation of the channel frequency;

a phase-locked-loop circuit, having an input for receiving the analog signal from the direct digital frequency synthesis circuit, and for producing a phase-modulated signal at an output.

21. The circuit of claim 20, wherein the direct digital frequency synthesis circuit comprises:

phase accumulator circuitry, for periodically combining a digital channel frequency word and a digital signal based on the phase digital signal to produce a digital phase accumulator output sequence;

a memory for producing a sine wave output sequence responsive to the phase accumulator output;

a digital-to-analog converter, for converting the sine wave output sequence into an analog signal.

22. The device of claim 20, wherein the direct digital frequency synthesis circuit comprises:

an accumulator for periodically accumulating a channel frequency word, the accumulator having an output corresponding to a most significant bit of the accumulator contents; and

edge correction and noise shaping circuitry, having an input receiving a sequence of the most significant bit of the accumulator contents, for adjusting the spacing of bit values in the sequence and applying a corresponding output signal to the phase-locked loop circuit.

23. The device of claim 20, wherein the most significant bit of the accumulator contents corresponds to a carry bit.