Semiconductor integrated circuit with resistor and method for fabricating thereof

• US 20030119243A1
• Filed: 01/28/2003
• Published: 06/26/2003
• Est. Priority Date: 11/23/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Won-Suk, Shin, Soo-Ho
• Granted Patent: US 6,656,791 B2
• Time in Patent Office: Days
• US Class Current: 438/200
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A resistor which have a stable resistance value and a method for fabricating the same without increasing the area of a semiconductor integrated circuit. To prevent a dishing phenomenon, the resistor is formed on the dummy gate electrode structure which have been formed in a peripheral circuit region and/or it is formed between a pair of dummy bit line structures. Regardless of a process condition the width and height of the resistor can be determined in a certain range with use of the capping layer and spacers of the dummy gate electrode structure and/or the capping layer and/or spacers of the dummy bit line structure.

Claims

1. A method for fabricating a semiconductor integrated circuit comprising the steps of:

preparing a semiconductor substrate including a cell array region and a peripheral circuit region;

forming a first insulating layer on the semiconductor substrate;

forming at least two or more dummy bit line structures on the first insulating layer belonging to the peripheral circuit region;

forming a resistor which is limited by the dummy bit line structures adjacent to it and is made of a conductive material.

2. The method for fabricating a semiconductor integrated circuit of claim 1 further comprising the step of forming a dummy gate electrode structure which is placed in the same level with the first insulating layer within the first insulating layer, between the step of preparing the semiconductor substrate and the step of forming the first insulating layer.

3. The method for fabricating a semiconductor integrated circuit of claim 1 further comprising the steps of forming a second insulating layer which covers the dummy bit line structures, between the step of forming the dummy bit line structure and the step of forming the resistor, wherein the step of forming the resistor includes the steps of:

forming an opening prepared for the resistor by etching a predetermined portion of the second insulating layer;

forming a conductive material layer on the semiconductor substrate including the opening; and

etching the conductive material layer until the top surfaces of the dummy bit line structures are exposed.

4. The method for fabricating a semiconductor integrated circuit of claim 2, wherein in the step of forming the dummy gate electrode structure a gate electrode structure placed in the same level with the first insulating layer is formed in the cell array region.

5. The method for fabricating a semiconductor integrated circuit of claim 1, wherein in the step of forming the dummy bit line structures in the peripheral circuit region, a bit line structure is also formed in the cell array region simultaneously and in the step of forming the resistor a self-alignment contact plug which is limited by the bit line structure adjacent to it, is formed in the cell array region simultaneously.

6. The method for fabricating a semiconductor integrated circuit of claim 1, wherein the first insulating layer is etched so as to extend the resistor to its inner part in the step of forming the resistor.

7. The method for fabricating a semiconductor integrated circuit of claim 1, wherein the first insulating layer is etched so as to extend the resistor to the semiconductor substrate under the first insulating layer in the step of forming the resistor.

8. The method for fabricating a semiconductor integrated circuit of claim 1, wherein the conductive material layer is polysilicon.