Semiconductor memory device

• US 20030119265A1
• Filed: 02/03/2003
• Published: 06/26/2003
• Est. Priority Date: 11/29/2000
• Status: Abandoned Application

• Current Assignee: Kazunobu Kuwazawa
• Original Assignee: Kazunobu Kuwazawa
• Inventors: Kuwazawa, Kazunobu
• Application Number:
  US10/357,111
• Publication Number:
  US 20030119265A1
• Time in Patent Office: Days
• US Class Current: 438/275
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved β ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.

Claims

1. A method for forming a semiconductor device comprising:

forming a pair of transfer MOS transistors controlled by a word line; and

forming a pair of data retaining flip-flop circuits from serially connected load elements and drive MOS transistors;

wherein the transfer MOS transistors are formed to have a threshold voltage greater than that of the drive MOS transistors.

2. A method for forming a semiconductor device as in claim 1, comprising:

implanting a first dose of an impurity ion into a channel region of each of the transfer MOS transistors;

implanting a second dose of an impurity ion into a channel region of each of the drive transistors;

wherein the first dose is greater than the second dose.

3. A method for forming a semiconductor device as in claim 1, further comprising introducing Ge into a gate electrode of each of the transfer MOS transistors.

4. A method for forming a semiconductor device comprising:

forming a pair of transfer MOS transistors controlled by a word line;

forming a pair of data retaining flip-flop circuits from serially connected load elements and drive MOS transistors; and

forming a gate electrode of each of the transfer MOS transistors to have a lower impurity concentration than that of a gate electrode of each of the drive MOS transistors.

5. A method for forming a semiconductor device as in claim 4, comprising forming a channel region of each the transfer MOS transistors to have an impurity concentration that is the same as that of a channel region of each of the drive MOS transistors.

6. A method for forming a semiconductor device including an SRAM, comprising:

forming a first transistor to include a gate electrode connected to a word line and to include a first end connected to a first bit line;

forming a second transistor to include a gate electrode connected to the word line and to include a first end connected to a second bit line;

forming a third transistor to include a gate electrode and to include a first end connected to a ground potential and a second end connected to a second end of the first transistor;

forming a fourth transistor to include a gate electrode and to include a first end connected to the ground potential and a second end connected to a second end of the second transistor;

forming a fifth transistor to include a gate electrode and to include a first end connected to a power supply and a second end connected to the second end of the first transistor;

forming a sixth transistor to include a gate electrode and to include a first end connected to the power supply and a second end connected to the second end of the second transistor;

forming the gate electrode of the third transistor and the gate electrode of the fifth transistor to each be connected to the second end of the second transistor;

forming the gate electrode of the fourth transistor and the gate electrode of the sixth transistor to each be connected to the second end of the first transistor; and

forming the first and second transistors to have a threshold voltage that is greater than a threshold voltage of the third and fourth transistors.

7. A method for forming a semiconductor device as in claim 6, further comprising supplying a power supply voltage in the range of 1.8 V to 2.5 V, a threshold voltage in the range of 0.75 V to 0.95 V for the first and second transistors, and a threshold voltage in the range of 0.6 V to 0.8 V for the third and fourth transistors.

8. A method for forming a semiconductor device as in claim 6, further comprising:

forming the first and second transistors to each include a channel region having an impurity ion implanted therein;

forming the third and fourth transistors to each include a channel region having an impurity implanted therein; and

providing a dose of an impurity ion implanted into the channel regions of the first and second transistors that is greater than a dose implanted into the channel regions of the third and fourth transistors.

9. A method for forming a semiconductor device as in claim 8, further comprising:

forming the gate electrode for each of the first, second, third and fourth transistors to include polysilicon and forming each of the first, second, third and fourth transistors to include a gate dielectric layer comprising silicon oxide having a thickness of approximately 4.5 nm; and

providing a P-type impurity concentration for the channel regions of the first and second transistors that is approximately 4×

10¹⁷ cm<sup>−

3</sup>, and a P-type impurity concentration for the channel regions of the third and fourth transistors that is approximately 3×

10¹⁷ cm<sup>−

3</sup>.

10. A method for forming a semiconductor device as in claim 6, further comprising forming the first and second transistor gate electrodes to each comprise polysilicon and germanium.

11. A method for forming a semiconductor device as in claim 10, further comprising forming the first and second transistor gate electrodes to each comprise polysilicon with germanium implanted therein, wherein the germanium concentration is 20 to 50 percent that of the silicon.

12. A method for forming a semiconductor device as in claim 6, further comprising forming the first and second transistor gate electrodes to each include an impurity concentration that is less than that of the third and fourth transistor gate electrodes.

13. A method for forming a semiconductor device as in claim 12, further comprising forming the impurity concentration of the first and second transistor gate electrodes to be in the range of 1×

10¹⁹ cm<sup>−

3</sup> to 5×

10¹⁹ cm<sup>−

3</sup>, and the impurity concentration of the third and fourth transistor gate electrodes to be in the range of 1×

10²⁰ cm<sup>−

3</sup> to 6×

10²⁰ cm<sup>−

3</sup>.

14. A method for forming a semiconductor device as in claim 12, further comprising:

forming the first and second transistors to each include a channel region having an impurity ion implanted therein;

forming the third and fourth transistors to each include a channel region having an impurity implanted therein; and

providing an impurity concentration in the channel regions of the first and second transistors that is approximately the same as an impurity concentration of the channel regions of the third and fourth transistors.