Three dimensional device integration method and integrated device

• US 20030119279A1
• Filed: 10/15/2002
• Published: 06/26/2003
• Est. Priority Date: 03/22/2000
• Status: Active Grant

• Current Assignee: Invensas Bonding Technologies, Inc. (Adeia Inc.)
• Original Assignee: Ziptronix Incorporated (Adeia Inc.)
• Inventors: Enquist, Paul M.
• Granted Patent: US 7,037,755 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/02008 : for solar cells or solar cell modules
• CPC Class Codes: H01L 31/043 : Mechanically stacked PV cells
• CPC Class Codes: H01L 31/0465 : comprising particular structures for the electrical interconnection of adjacent PV cells in the module H01L31/0463 takes precedence
• CPC Class Codes: Y02E 10/50 : Photovoltaic [PV] energy

Abstract

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

Claims

1. A method of forming an integrated device, comprising:

forming a first bonding material on a first semiconductor device having a first substrate;

forming a second bonding material on a first element having a second substrate;

directly bonding said first and second bonding materials;

removing a portion of said first substrate to expose a remaining portion of said first semiconductor device; and

mounting said integrated device in a package.

2. A method as recited in claim 1, comprising:

connecting said package to said first semiconductor device from an exposed side of said remaining portion of said first semiconductor device.

3. A method as recited in claim 1, comprising:

bonding said first semiconductor device having said first substrate with top and bottom sides, an active area being formed in said top side;

removing said portion from said bottom side; and

connecting said package to said first semiconductor device from said bottom side.

4. A method as recited in claim 3, comprising:

directly bonding a second element having a third substrate to said remaining portion of said first semiconductor device;

removing substantially all of said first element; and

connecting said first semiconductor device to said package from said top side.

5. A method as recited in claim 3, comprising:

forming a plurality of levels of interconnect in said first semiconductor device; and

forming connections to at least one of said levels of interconnect from an exposed remaining portion side; and

interconnecting said connections with said package.

6. A method as recited in claim 5, wherein forming connections comprises:

forming a plurality of levels of interconnect from an exposed remaining portion side.

7. A method as recited in claim 3, comprising:

directly bonding a third substrate to said remaining portion of said first semiconductor device;

exposing portions of said first semiconductor device from said top side; and

connecting said semiconductor device to said package from said top side through said third substrate.

8. A method as recited in claim 7, wherein said first semiconductor device comprises a plurality of levels of interconnect;

said method comprising;

forming connections to at least one of said levels of interconnect from an exposed remaining portion side; and

interconnecting said connections with said package.

9. A method as recited in claim 1, comprising:

forming a connection directly to a device element region of said first semiconductor device.

10. A method of forming an integrated device, comprising:

bonding a first thermal spreading substrate to a first semiconductor device having a device substrate;

removing a portion of said device substrate to expose a remaining portion of said first semiconductor device; and

bonding a second thermal spreading substrate to said remaining portion of said first semiconductor.

11. A method as recited in claim 10, comprising:

forming a plurality of levels of interconnect in said first semiconductor device; and

forming connections to at least one of said levels of interconnect using said first thermal spreading substrate.

12. A method as recited in claim 11, comprising:

forming connections to at least one of said levels of interconnect using an areal contacting method.

13. A method as recited in claim 11, comprising:

forming a connection directly to a device element region of said first semiconductor device.

14. A method as recited in claim 10, comprising:

forming a plurality of levels of interconnect in said first semiconductor device; and

forming connections to at least one of said levels of interconnect using said second thermal spreading substrate.

15. A method as recited in claim 14, comprising:

forming connections to at least one of said levels of interconnect using an areal contacting method.

16. A method as recited in claim 10, comprising:

forming interconnect structures in said semiconductor device accessible from a side exposed by removing said portion before said step of removing said portion.

17. A method as recited in claim 10, comprising:

forming interconnect structures in said semiconductor device, accessible from a side exposed by removing said portion, using processing from a side opposite said side exposed by removing said portion.

18. A method of forming an integrated device, comprising:

directly bonding a first semiconductor device having a first substrate to an element; and

removing a portion of said first substrate to expose a remaining portion of said first semiconductor device after said bonding;

wherein said element comprises one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements.

19. A method as recited in claim 18, comprising:

removing a portion of said remaining portion to expose a portion of said element.

20. A method as recited in claim 19, comprising:

interconnecting said remaining portion of said first semiconductor device with said element.

21. A method of forming an integrated system, comprising:

directly bonding a first component of a system to a second component of a system; and

interconnecting said first and second components.

22. A method as recited in claim 21, comprising:

bonding said first component to a second component having a substrate;

removing at least a portion of said substrate from a side of said second component; and

interconnecting said first and second components from said side of said second component.

23. A method as recited in claim 21, comprising:

bonding one of a shielding member and an isolation member to at least one of said first and second components.

24. A method as recited in claim 21, comprising:

bonding an antenna to at least one of said first and second components; and

connecting said antenna to at least one said first and second components.

25. A method as recited in claim 21, comprising

bonding an optical device as said first component to an electrical device as said second component.

26. A method as recited in claim 21, comprising:

bonding a lower-speed higher-density first semiconductor device as said first component to a higher-speed lower-density second semiconductor device as said second component.

27. A method as recited in claim 26, comprising:

bonding said first and second semiconductor devices of different technologies.

28. A method as recited in claim 26, comprising:

bonding a silicon device as said first semiconductor device to at least one III-V device as said second semiconductor device.

29. A method as recited in claim 21, comprising:

bonding a microprocessor on a first substrate comprising said first component to a high density memory device comprising said second component.

30. A method as recited in claim 21, comprising:

bonding a first solar cell comprising said first component to a second solar cell comprising said second component.

31. A method as recited in claim 30, comprising:

bonding at least a third solar cell to an element formed by bonding said first and second solar cells.

32. A method as recited in claim 21, comprising:

forming a void in a surface of said first component;

bonding said surface of said first component to a surface of said second component.

33. A method of integrating devices, comprising:

attaching a plurality of first elements to a surface of a substrate to form a second element; and

directly bonding said second element, from a side to which said plurality of first elements are attached, to a third element.

34. A method as recited in claim 33, wherein attaching comprises:

directly bonding each of said plurality of first elements to said surface of said substrate to form said second element.

35. A method as recited in claim 34, comprising:

removing at least a portion of said second element after bonding said second element to said third element.

36. A method as recited in claim 34, comprising:

directly bonding a plurality of first semiconductor devices to said surface of said substrate; and

directly bonding said second element to a third element comprising a second semiconductor device.

37. A method as recited in claim 34, comprising:

interconnecting said first elements with said third element.

38. A method as recited in claim 34, comprising:

interconnecting said first elements using said second element; and

interconnecting said first elements and said third element using at least one of said second and third elements.

39. A method as recited in claim 34, comprising:

forming recesses in said second element; and

bonding said plurality of first elements to said second element in said recesses.

40. A method as recited in claim 39, comprising:

removing at least a portion of said second element after bonding said second element to said third element.

41. A method as recited in claim 39, comprising:

directly bonding a plurality of first semiconductor devices to said surface of said substrate; and

directly bonding said second element to a third element comprising a second semiconductor device.

42. A method as recited in claim 39, comprising:

interconnecting said first elements with said third element.

43. A method as recited in claim 39, comprising:

interconnecting said first elements using said second element; and

interconnecting said first elements and said third element using at least one of said second and third elements.

44. A method as recited in claim 34, comprising:

directly bonding first semiconductor devices, as said first elements, on substrates; and

directly bonding said first semiconductor devices to, as said second element;

at least one of a substrate used for thermal spreading, impedance matching, RF isolation, antenna, a second semiconductor device, and a matching network comprised of at least one of passive elements and conductive layer patterning.

45. A method as recited in claim 44, comprising:

removing at least a portion of said substrates on which said first semiconductor devices are bonded.

46. A method as recited in claim 44, comprising:

interconnecting said first semiconductor devices with said second element.

47. A method of forming an integrated device, comprising:

forming a first bonding material on a first semiconductor device having a first substrate;

forming a second bonding material on a second element having a second substrate;

directly bonding said first and second bonding materials;

forming a conductor array having a plurality of contact structures on an exposed surface of said first semiconductor device;

forming vias through said first semiconductor device to device regions; and

forming interconnection between said device regions and said contact structures.

48. A method as recited in claim 47, comprising:

forming a pin grid array as said conductor array.

49. A method as recited in claim 48, comprising:

mating said pin grid array with conductive regions formed on one of a board, card, and substrate.

50. A method as recited in claim 47, comprising:

mating said conductor array with conductive regions formed on at least one of a board, card, and substrate.

51. An integrated device, comprising:

a first device portion comprised of a first device having a first substrate from which said first substrate has been removed;

a first bonding material formed on said first device portion;

a first element;

a second bonding material formed on said first element; and

said first bonding material directly bonded to said second bonding material.

52. An integrated device as recited in claim 51, wherein:

said first device portion comprises a first solar cell portion comprised of a first solar cell having said first substrate from which said first substrate has been removed;

said first element comprises a second solar cell having a second substrate; and

said integrated device comprising interconnections formed connecting said first solar cell portion and said second solar cell from a side of said first solar cell portion from which said first substrate is removed.

53. An integrated device as recited in claim 52, comprising:

at least a third solar cell portion, formed by removing a third substrate from a third solar cell;

a third bonding material formed on said third solar cell portion;

a fourth bonding material formed on said side of said first solar cell portion;

interconnections connecting said first solar cell portion, said second solar cell and said third solar cell portion formed from a side of said third solar cell portion from which said third substrate is removed.

54. An integrated device as recited in claim 51, wherein:

said first device portion comprises a semiconductor device having active elements; and

said first element comprises one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements.

55. An integrated device as recited in claim 51, wherein:

said first device portion comprises a remaining portion, having a first side and an opposing second side, of a first wafer having a first substrate from which substantially all of said first substrate has been removed from said first side of said remaining portion; and

said first element is directly bonded to said second side of said remaining portion.

56. An integrated defice as recited in claim 55, comprising:

an interconnection connected to said first device portion from said first side.

57. An integrated device as recited in claim 56, wherein said interconnection comprises a multilayer interconnection.

58. An integrated device as recited in claim 55, wherein:

said remaining portion comprises no more than 10 microns of said first substrate.

59. An integrated device as recited in claim 55, wherein:

said remaining portion comprises no more than 20 microns of said first substrate.

60. An integrated device as recited in claim 55, comprising:

a package connected to said first device portion from said first side.

61. An integrated device as recited in claim 51, wherein:

said first device portion comprises a remaining portion, having a first side and an opposing second side, of a first wafer having a first substrate from which said first substrate has been substantially removed from said first side of said remaining portion; and

said first element is directly bonded to said first side of said remaining portion.

62. An integrated device as recited in claim 61, comprising:

an interconnection connected to said first device portion from said first side.

63. An integrated device as recited in claim 62, wherein said interconnection comprises a multilayer interconnection.

64. An integrated device as recited in claim 63, comprising:

a package connected to said first device from said second side.

65. An integrated device as recited in claim 51, wherein:

said first device portion comprises one of an active area of a memory and an active area of a microprocessor; and

said first element comprises one of a microprocessor device and a memory device, respectively; and

said integrated device comprises interconnections formed between said first device portion and said first element.

66. An integrated device as recited in claim 51, comprising:

one of a shielding member and an isolation member directly bonded to at least one of said first device portion and said first element.

67. An integrated device as recited in claim 51, comprising:

an antenna directly bonded to at least one of said first device portion and said first element; and

interconnections connecting said antenna to at least one said first device portion and said first element.

68. An integrated device as recited in claim 51, wherein:

said first device portion comprises an optical device; and

said first element comprises one of an electrical device and circuit.

69. An integrated device as recited in claim 51, wherein:

said first element comprises a lower-speed higher-density first semiconductor device; and

said first device portion comprises a higher-speed lower-density second semiconductor device.

70. An integrated device as recited in claim 69, comprising:

said first and second semiconductor devices being different technologies.

71. An integrated device as recited in claim 51, wherein:

said first element comprises a silicon processor; and

said first device portion comprises a III-V device.

72. An integrated device, comprising:

a plurality of first elements each directly bonded to a surface of substrate to from a second element; and

a third element directly bonded to said second elements from a side on which said first elements are bonded to said surface.

73. A device as recited in claim 72, comprising:

interconnections formed between said third element and selected ones of said plurality of first elements.

74. A device as recited in claim 72, comprising:

interconnections formed between selected ones of said plurality of first elements.

75. A device as recited in claim 72, comprising:

recesses formed in said substrate; and

said first elements being disposed in said recesses.

76. An integrated device, comprising:

a device portion containing semiconductor devices having opposing top and bottom sides;

a first substrate directly bonded to said top side of said device portion; and

a second substrate directly bonded to said bottom side of said device portion.

77. A device as recited in claim 76, comprising:

interconnections formed to said device portion through each of said first and second substrates.

78. A device as recited in claim 76, comprising:

power and ground interconnections formed to said device portion through only one of said first and second substrates.

79. A device as recited in claim 78, comprising:

at least one of signal and clock interconnections formed to said device portion through only the other of said first and second substrates.

80. A device as recited in claim 76, wherein said device portion comprises a plurality of device portions directly bonded to each other.

81. An integrated device, comprising:

a plurality of first elements each directly bonded to a surface of a second element.

82. A device as recited in claim 81, wherein:

first elements comprise at least one of first semiconductor devices, first patterned conductors, first antenna elements, and first impedance matching elements with passive components; and

said second element comprises at least one of second semiconductor devices, second patterned conductors, second antenna elements, and second impedance matching elements with passive components.

83. A device as recited in claim 82, wherein said first elements comprise at least one of said first semiconductor devices, first patterned conductors, first antenna elements, and first impedance matching elements with passive components from which a substrate was removed.

84. A device as recited in claim 83, comprising:

vias formed in said first elements; and

conductive material formed in said vias interconnecting said first elements to said second element.

85. An integrated device, comprising:

a first bonding material disposed on a first semiconductor device having a first substrate and first conductive regions;

a second bonding material disposed on a first element having a second substrate and directly bonded to the first bonding material;

a conductive array disposed on an exposed surface of first element having a plurality of second conductive regions; and

interconnection formed between said first and second conductive regions.

86. A device as recited in claim 85, wherein said conductive array comprises a pin grid array.

87. A device as recited in claim 86, comprising:

conducting regions formed on at least one of a board, card, and substrate mated with said second conductive regions.

88. A device as recited in claim 85, comprising:

conducting regions formed on at least one of a board, card, and substrate mated with said second conductive regions.