Contactless nor-type memory array and its fabrication Methods

• US 20030122181A1
• Filed: 12/27/2001
• Published: 07/03/2003
• Est. Priority Date: 12/27/2001
• Status: Active Grant

• Current Assignee: Ching-Yuan Wu
• Original Assignee: Ching-Yuan Wu
• Inventors: Wu, Ching-Yuan
• Granted Patent: US 6,703,661 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A contactless NOR-type memory array of the present invention comprises a plurality of integrated floating-gate layers formed on a shallow-trench isolation structure, a plurality of word lines having an interlayer dielectric layer formed on an elongated control-gate layer for each word line, a plurality of common-source bus lines having a silicided conductive layer formed over a flat bed for each common-source line and, a plurality of bit lines with each bit line being integrated with a plurality of silicided conductive islands formed on the common-drain diffusion regions. The contactless NOR-type memory array of the present invention may offer: a cell size of 4F², no contact problems for shallow source/drain junction of the cell, lower common-source bus line resistance and capacitance, and better density*speed*power product as compared to existing NAND-type memory array.

Claims

1. A contactless NOR-type memory array, comprising:

a semiconductor substrate of a first conductivity type;

a plurality of parallel isolation regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein a raised field-oxide film is formed on each of the plurality of parallel isolation regions and a thin tunneling dielectric layer is formed over each of the plurality of active regions;

a plurality of word lines being formed alternately on said semiconductor substrate and transversely to the plurality of parallel isolation regions, wherein each of the plurality of word lines comprises an elongated control-gate layer being sandwiched between an interlayer dielectric layer formed on the top and an intergate dielectric layer formed at the bottom, and a plurality of integrated floating-gate layer being formed beneath said intergate dielectric layer;

wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer being formed on said thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of each of two nearby raised field-oxide films;

a plurality of common-source diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-source lines, wherein each of the plurality of common-source lines is situated in every two of said word lines and between a pair of said word lines;

a plurality of common-drain diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-drain lines, wherein each of the plurality of common-drain lines is situated between a pair of said word lines formed between a pair of said common-source lines;

a plurality of flat beds being located in the plurality of common-source lines, wherein said raised field-oxide films along each of the plurality of common-source lines are etched and each of the plurality of flat beds is formed alternately by the plurality of common-source diffusion regions and said etched raised field-oxide films;

a plurality of first dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of flat beds, and a plurality of second dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films along the plurality of common-drain lines;

a plurality of silicided common-source conductive layers being situated on the plurality of common-source lines, wherein each of the plurality of silicided common-source conductive layers is formed over said flat bed between a pair of said first dielectric spacers with a second thick-oxide layer formed on the top;

a plurality of silicided common-drain conductive islands being situated on the plurality of common-drain lines, wherein each of the plurality of silicided common-drain conductive islands is formed between a pair of said second dielectric spacers and on a portion of each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films along each of the plurality of common-drain lines; and

a plurality of bit lines being formed above the plurality of active regions and transversely to the plurality of word lines, wherein each of the plurality of bit lines is formed over a flat surface formed alternately by said second thick-oxide layer, said interlayer dielectric layer, and said silicided common-drain conductive island having a hard masking layer formed on a metal layer to simultaneously pattern and form said metal layer and said silicided common-drain conductive islands along each of the plurality of bit lines.

2. The contactless NOR-type memory array according to claim 1, wherein the plurality of parallel isolation regions are formed by using shallow-trench-isolation (STI) techniques.

3. The contactless NOR-type memory array according to claim 1, wherein the plurality of parallel isolation regions are formed by using local-oxidation of silicon (LOCOS) techniques.

4. The contactless NOR-type memory array according to claim 1, wherein said elongated control-gate layer is preferably a composite conductive layer having a refractory-metal silicide layer formed over a doped polycrystalline-silicon layer.

5. The contactless NOR-type memory array according to claim 1, wherein said interlayer dielectric layer is preferably a compositive dielectric layer having a capping silicon-nitride layer formed on a first thick-oxide layer, a silicon-oxynitride layer or an insulator layer of low dielectric constant.

6. The contackless NOR-type memory array according to claim 1, wherein said intergate dielectric layer is preferably a composite dielectric layer having a n oxide-nitride-oxide structure or a nitride-oxide structure.

7. The contactless NOR-type memory array according to claim 1, wherein said integrated floating-gate layer is preferably made of doped polycrystalline-silicon or doped amorphous-silicon.

8. The contactless NOR-type memory array according to claim 1, wherein said first dielectric spacer and said second dielectric spacer are preferably made of silicon-oxides, silicon-oxynitrides, silicon-nitrides, or dielectric materials of low dielectric constant.

9. The contactless NOR-type memory array according to claim 1, wherein said silicided common-source conductive layer and said silicided common-drain conductive island are preferably a refractory-metal silicide layer formed on a doped polycrystalline-silicon or doped amorphous-silicon layer,

10. The contactless NOR-type memory array according to claim 1, wherein said metal layer is preferably aluminum (Al), copper (Cu), tungsten (W), or tungsten-silicide (WSi₂) on a barrier-metal layer such as TiN or TaN.

11. The contactless NOR-type memory array according to claim 1, wherein said hard masking layer comprises a masking dielectric layer and its two sidewall dielectric spacers and is preferably made of silicon-nitrides or silicon-oxides or silicon-oxynitrides.

12. The contactless NOR-type memory array according to claim 1, wherein said common-source diffusion region is preferably a double-diffused structure having a heavily-doped source diffusion region of said second conductivity type formed within a lightly-doped source diffusion region of said second conductivity type and said common-drain diffusion region is preferably a heavily-doped drain diffusion region of said second conductivity type.

13. The contactless NOR-type memory array according to claim 1, wherein said common-source diffusion region is preferably a double-diffused structure having a heavily-doped source diffusion region of said second conductivity type formed within a lightly-doped source diffusion region of said second conductivity type and said common-drain diffusion region is preferably a double-diffused structure having a heavily-doped diffusion region of said second conductivity type formed within a lightly-doped diffusion region of said first conductivity type.

14. The contactless NOR-type memory array according to claim 1, wherein said common-source diffusion region and said common-drain diffusion region are preferably a double-diffused structure having a heavily-doped source/drain diffusion region of said second conductivity type formed within a lightly-doped source/drain diffusion region of said second conductivity type.

15. A contactless NOR-type memory array, comprising:

a semiconductor substrate of a first conductivity type;

a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein a raised field-oxide film is formed on each of the plurality of parallel STI regions and a thin tunneling-dielectric layer is formed over each of the plurality of active regions;

a plurality of word lines being formed alternately on said semiconductor substrate and transversely to the plurality of parallel STI regions, wherein each of the plurality of word lines comprises an elongated polycide-gate layer being sandwiched between a capping silicon-nitride layer over a first thick-oxide layer formed on the top and an intergate dielectric layer formed at the bottom, and a plurality of integrated floating-gate layers being formed beneath said intergate dielectric layer;

wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer formed on said thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of each of two nearby raised field-oxide films;

a plurality of common-source diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-source lines, wherein each of the plurality of common-source lines is situated in every two of said word lines and between a pair of said word lines and each of the plurality of common-source diffusion regions comprises a heavily-doped diffusion region of a second conductivity type formed within a lightly-doped diffusion region of said second conductivity type;

a plurality of common-drain diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-drain lines, wherein each of the plurality of common-drain lines is situated between a pair of said word lines formed between a pair of said common-source lines and each of the plurality of common-drain diffusion regions comprises a heavily-doped diffusion region of said second conductivity type;

a plurality of flat beds being located in the plurality of common-source lines, wherein said raised field-oxide films along each of the plurality of common-source lines are etched and each of the plurality of flat beds is formed alternately by the plurality of common-source diffusion regions and said etched raised field-oxide films;

a plurality of first dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of flat beds, and a plurality of second dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films along each of the plurality of common-drain lines;

a plurality of heavily-doped polycrystalline-silicon layer capped with a first silicide layer being situated on the plurality of common-source lines, wherein each of the plurality of heavily-doped polycrystalline-silicon layers is formed over said flat bed between a pair of said first dielectric spacers having a second thick-oxide layer formed on the top of said first silicide layer;

a plurality of heavily-doped polycrystalline-silicon islands capped with a second silicide layer being situated on the plurality of common-drain lines, wherein each of the plurality of heavily-doped polycrystalline-silicon islands is formed between a pair of said second dielectric spacers and on a portion of each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films formed nearby; and

a plurality of bit lines being formed above the plurality of active regions and transversely to the plurality of word lines having each of the plurality of bit lines formed over a flat surface formed alternately by said second thick-oxide layer, said capping silicon-nitride layer, and said second silicide layer, wherein each of the plurality of bit lines comprises a hard masking layer being formed on a metal layer and said hard masking layer including a masking dielectric layer and its two sidewall dielectric spacers is used to simultaneously pattern and form said metal layer and said second silicide layer, and said heavily-doped polycrystalline-silicon islands along each of the plurality of bit lines.

17. The contactless NOR-type memory array according to claim 15 or claim 16, wherein said first dielectric spacer and said second dielectric spacer are preferably made of silicon-oxides, silicon-oxynitrides, silicon-nitrides or dielectric materials of low dielectric constant.

18. The contactless NOR-type memory array according to claim 15 or claim 16, wherein said first silicide layer and said second silicide layer are preferably made of refractory-metal silicides such as TiSi₂, CoSi₂, TaSi₂, MoSi₂, NiSi₂, WSi₂ or PtSi₂ etc.

19. The contacless NOR-type memory array according to claim 15 or claim 16, wherein said metal layer is preferably consisting of aluminum (Al), copper (Cu), tungsten (W) or tungsten-silicide (Wsi₂) formed over a barrier-metal layer.

20. The contactless NOR-type memory array according to claim 15 or clam 16, wherein said hard masking layer including a masking dielectric layer and its two sidewall dielectric spacer are preferably made of silicon-nitrides, silicon-oxynitrides or silicon-oxides.

16. A contactless NOR-type memory array, comprising:

a semiconductor substrate of a first conductivity type;

a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein a raised field-oxide film is formed on each of the plurality of parallel STI regions and a thin tunneling-dielectric layer is formed over each of the plurality of active regions;

a plurality of word lines being formed alternately on said semiconductor substrate and transversely to the plurality of parallel STI lines, wherein each of the plurality of word lines comprises an elongated polycide-gate layer being sandwiched between a capping silicon-nitride layer over a first thick-oxide layer formed on the top and an intergate dielectric layer formed at the bottom, and a plurality of integrated floating-gate layers being formed beneath said intergate dielectric layer;

wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer formed on said thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of each of two nearby raised field-oxide films;

a plurality of common-source diffusion regions being formed in said semiconductor substrate of the plurality of active regions along a plurality of common-source lines, wherein each of the plurality of common-source lines is situated between a pair of said word lines formed between a pair of said common-source lines and each of the plurality of common-source diffusion regions comprises a heavily-doped diffusion region of a second conductivity type formed within a lightly-doped diffusion region of said second conductivity type;

a plurality of common-drain diffusion regions being formed along the plurality of common-drain lines, wherein each of the plurality of common-drain diffusion regions comprises a heavily-doped diffusion region of said second conductivity type formed within a lightly-doped diffusion region of said first conductivity type;

a plurality of flat beds being located in the plurality of common-source lines, wherein said raised field-oxide films along each of the plurality of common-source lines are etched and each of the plurality of flat beds is formed alternately by the plurality of common-source diffusion regions and said etched raised field-oxide films;

a plurality of first dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of flat beds, and a plurality of second dielectric spacers being formed over the sidewalls of the plurality of word lines and on a portion of each of the plurality of common-drain diffusion regions and a portion said raised field-oxide films along each of the plurality of common-drain lines;

a plurality of heavily-doped polycrystalline-silicon layers capped with a first silicide layer being situated on the plurality of common-source lines, wherein each of the plurality of heavily-doped polycrystalline-silicon layers is formed over said flat bed between a pair of said first dielectric spacers having a second thick-oxide layer formed on the top of said first silicide layer;

a plurality of heavily-doped polycrystalline-silicon islands capped with a second silicide layer being situated on the plurality of common-drain lines, wherein each of the plurality of heavily-doped polycrystalline-silicon islands is formed between a pair of said second dielectric spacers and on a portion of each of the plurality of common-drain diffusion regions and a portion of said raised field-oxide films formed nearby; and

a plurality of bit lines being formed above the plurality of active regions and transversely to the plurality of word lines having each of the plurality of bit lines formed over a flat surface formed alternately by said second thick-oxide layer over said first silicide layer, said capping silicon-nitride layer over said first thick-oxide layer over said elongated polycide-gate layer, and said second silicide layer over said heavily-doped polycrystalline-silicon islands, wherein each of the plurality of bit lines comprises a hard masking layer being formed on a metal layer and said hard masking layer including a masking dielectric layer and its two sidewall dielectric spacers is used to simultaneously pattern and form said metal layer, said second silicide layer, and said heavily-doped polycrystalline-silicon islands along each of the plurality of bit lines.