Charge pump ripple reduction

• US 20030122610A1
• Filed: 06/27/2002
• Published: 07/03/2003
• Est. Priority Date: 01/02/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Zeng, Raymond W., Annavajjhala, Ravi P., Yuvienco, Mary Frances Therese B.
• Granted Patent: US 6,836,176 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/077 with parallel connected charge pump stages

Abstract

A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.

Claims

1. An apparatus comprising:

a frequency synthesis device;

a pump cell connected to the frequency synthesis device; and

a feedforward circuit connected to the frequency synthesis device to selectively activate and deactivate the frequency synthesis device in response to a pump cell output signal.

2. The apparatus of claim 1, wherein the feedforward circuit includes a comparator or a differential amplifier.

3. The apparatus of claim 1, further comprising a differential amplifier to bias the frequency synthesis device.

4. The apparatus of claim 1, wherein the frequency synthesis device includes a voltage controlled oscillator.

5. The apparatus of claim 1, wherein the frequency synthesis device comprises a voltage controlled oscillator and a clock driver.

6. The apparatus of claim 2, wherein the feedforward circuit is connected to a voltage controlled oscillator and a clock driver.

7. The apparatus of claim 3, wherein the frequency synthesis device comprises a voltage controlled oscillator and a clock driver.

8. The apparatus of claim 4, wherein the frequency synthesis device further comprises a clock driver.

9. The apparatus of claim 1, wherein the feedforward circuit is to selectively activate or deactivate the frequency synthesis device in response to both the pump cell output signal and a reference signal.

10. The apparatus of claim 1, further comprising an electrically-erasable programmable read-only memory coupled to the pump cell output.

11. The apparatus of claim 1, further comprising a biasing circuit to drive the frequency synthesis device in response to both the pump cell output signal and a reference signal.

12. The apparatus of claim 9, further comprising a biasing circuit to drive the frequency synthesis device in response to both the pump cell output signal and a reference signal.

13. A method comprising:

receiving a feedback signal from a pump cell output;

generating a feedforward signal;

selectively activating or deactivating a frequency synthesis device coupled to the pump cell in response to the feedforward signal.

14. The method of claim 13, further comprising comparing the feedback signal with a second signal to generate the feedforward signal.

15. The method of claim 13, further comprising differentially amplifying the feedback signal and a second signal to create a biasing signal for the frequency synthesis device.

16. The method of claim 14, wherein the second signal is a reference signal.

17. The method of claim 13, further comprising transmitting the feedforward signal to a voltage controlled oscillator and a clock driver.

18. The method of claim 14, further comprising transmitting the feedforward signal to a voltage controlled oscillator and a clock driver.

19. The method of claim 15, further comprising transmitting the feedforward signal to a voltage controlled oscillator and a clock driver.

20. The method of claim 16, further comprising transmitting the feedforward signal to a voltage controlled oscillator and a clock driver.

21. The method of claim 13, wherein the selective activation or deactivation is in response to both a pump cell output signal and a second signal.

22. The method of claim 13, further comprising programming an electrically-erasable programmable read-only memory with current supplied by the pump cell.

23. The method of claim 13, further comprising biasing a frequency synthesis device in response to the pump cell output signal and a second signal.

24. The method of claim 15, wherein, in a first condition, the frequency synthesis device is to be activated or deactivated in response to the biasing signal and, in a second condition, the frequency synthesis device is to be activated or deactivated in response to the feedforward signal.

25. A system comprising:

a processor unit coupled to a bus;

a main memory unit coupled to the bus; and

a long term memory unit coupled to the bus, said long term memory unit comprising;

a frequency synthesis device,

a pump cell connected to the frequency synthesis device,

a feedforward circuit connected to the frequency synthesis device to selectively activate and deactivate the frequency synthesis device in response to a pump cell output signal, and

a plurality of electrically-erasable programmable read-only memory cells coupled to the pump cell output.

26. The system of claim 25, wherein the feedforward circuit includes a comparator or a differential amplifier.

27. The system of claim 25, wherein the long term memory unit further comprises a differential amplifier to bias the frequency synthesis device.

28. The system of claim 25, wherein the frequency synthesis device includes a voltage controlled oscillator.