Semiconductor integrated circuit and semiconductor memory

• US 20030123276A1
• Filed: 10/15/2002
• Published: 07/03/2003
• Est. Priority Date: 12/28/2001
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Yokozeki, Wataru
• Granted Patent: US 6,738,281 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0072 and the nonvolatile element is a ferroelectric element

Abstract

Inputs of two buffer circuits which constitute a latch circuit receive different voltages due to a capacitance coupling effect of ferroelectric capacitors or capacitance division of the ferroelectric capacitors, before connected with power source. After the power turns on, a switch control circuit activates switch control signals when a first plate voltage rises to a predetermined voltage. Switch circuits turn on in response to the activation of the switch control signals, and connect power source terminals of the buffer circuits to a power source line. At this time, input voltages of the buffer circuits are different from each other, and therefore, logic data is written into the latch circuit according to each of the input voltages. As a result of this, data held in the latch circuit before turning-off of the power can be reproduced without fail.

Claims

1. A semiconductor integrated circuit comprising:

a latch circuit having two buffer circuits whose inputs and outputs are connected to each other;

a pair of ferroelectric capacitors whose one ends are respectively connected to the inputs of said buffer circuits and the other ends are connected to a first plate line;

switch circuit(s) for connecting power supply terminals of said buffer circuits to power source line(s) according to switch control signal(s);

a first plate voltage generator for generating a first plate voltage to be supplied to said first plate line; and

a switch control circuit for activating said switch control signal(s) and turning on said switch circuit(s), when said first plate voltage rises to a predetermined voltage after the power turns on.

2. The semiconductor integrated circuit according to claim 1, wherein:

each of said buffer circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor;

a source of said pMOS transistor is connected to one of said power source lines through one of said switch circuits;

a source of said nMOS transistor is connected to a ground line, which is the other of said power source lines, through the other of said switch circuits;

a substrate of said PMOS transistor is connected to said power source line; and

a substrate of said nMOS transistor is connected to said ground line.

3. A semiconductor integrated circuit comprising:

a latch circuit having two buffer circuits whose inputs and outputs are connected to each other;

a pair of first ferroelectric capacitors being connected in series between a first plate line and a second plate line, wherein an intermediate node connecting the pair of first ferroelectric capacitors is connected to an input of one of said buffer circuits;

a pair of second ferroelectric capacitors being connected in series between said first plate line and said second plate line, wherein an intermediate node connecting the pair of second ferroelectric capacitors is connected to an input of the other of said buffer circuits;

switch circuit(s) for connecting power supply terminals of said buffer circuits to power source line(s) according to switch control signal(s);

a first plate voltage generator for generating a first plate voltage to be supplied to said first plate line;

a second plate voltage generator for generating a second plate voltage which is lower than said first plate voltage and is supplied to said second plate line for a predetermined period after the power turns on; and

a switch control circuit for activating said switch control signal(s) and turning on said switch circuit(s), when said first plate voltage rises to a predetermined voltage after the power turns on.

4. The semiconductor integrated circuit according to claim 3, wherein

said second plate voltage generator outputs a ground voltage as said second plate voltage for at least said predetermined period.

5. The semiconductor integrated circuit according to claim 4, wherein:

each of said buffer circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor;

a source of said pMOS transistor is connected to one of said power source lines through one of said switch circuits;

a source of said nMOS transistor is connected to a ground line, which is the other of said power source lines, through the other of said switch circuits;

a substrate of said pMOS transistor is connected to said power source line; and

a substrate of said nMOS transistor is connected to said ground line.

6. A semiconductor integrated circuit having a storage circuit in which a master latch circuit and a slave latch circuit are cascaded, wherein at least one of said master latch circuit and said slave latch circuit comprise(s):

a latch circuit having two buffer circuits whose inputs and outputs are connected to each other;

a pair of ferroelectric capacitors whose one ends are respectively connected to the inputs of said buffer circuits and the other ends are connected to a first plate line;

switch circuit(s) for connecting power supply terminals of said buffer circuits to power source line(s) according to switch control signal(s);

a first plate voltage generator for generating a first plate voltage to be supplied to said first plate line; and

a switch control circuit for activating said switch control signal(s) and turning on said switch circuits, when said first plate voltage rises to a predetermined voltage after the power turns on.

7. The semiconductor integrated circuit according to claim 6, wherein:

each of said buffer circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor;

a source of said pMOS transistor is connected to one of said power source lines through one of said switch circuits;

a source of said nMOS transistor is connected to a ground line, which is the other of said power source lines, through the other of said switch circuits;

a substrate of said pMOS transistor is connected to said power source line; and

a substrate of said nMOS transistor is connected to said ground line.

8. A semiconductor integrated circuit having a storage circuit in which a master latch circuit and a slave latch circuit are cascaded, wherein at least one of said master latch circuit and said slave latch circuit comprise(s):

a latch circuit having two buffer circuits whose inputs and outputs are connected to each other;

a pair of first ferroelectric capacitors being connected in series between a first plate line and a second plate line, wherein an intermediate node connecting the pair of first ferroelectric capacitors is connected to an input of one of said buffer circuits;

a pair of second ferroelectric capacitors being connected in series between said first plate line and said second plate line, wherein an intermediate node connecting the pair of second ferroelectric capacitors is connected to an input of the other of said buffer circuits;

switch circuit(s) for connecting power supply terminals of said buffer circuits to power source line(s) according to switch control signal(s);

a first plate voltage generator for generating a first plate voltage to be supplied to said first plate line;

a second plate voltage generator for generating a second plate voltage which is lower than said first plate voltage and is supplied to said second plate line for a predetermined period after the power turns on; and

a switch control circuit for activating said switch control signal(s) and turning on said switch circuit(s), when said first plate voltage rises to a predetermined voltage after the power turns on.

9. The semiconductor integrated circuit according to claim 8, wherein said second plate voltage generator outputs a ground voltage as said second plate voltage for at least said predetermined period.

10. The semiconductor integrated circuit according to claim 8, wherein:

each of said buffer circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor;

a source of said pMOS transistor is connected to one of said power source lines through one of said switch circuits;

a source of said nMOS transistor is connected to a ground line, which is the other of said power source lines, through the other of said switch circuits;

a substrate of said pMOS transistor is connected to said power source line; and

a substrate of said nMOS transistor is connected to said ground line.

11. A semiconductor memory comprising:

a plurality of memory cells, each of which has a latch circuit having two inversion circuits whose inputs and outputs are connected to each other and a pair of ferroelectric capacitors whose one ends are respectively connected to the inputs of said inversion circuits and the other ends are connected to a first plate line;

switch circuit(s) for connecting power supply terminals of said inversion circuits to power source line(s) according to switch control signal(s);

a first plate voltage generator for generating a first plate voltage to be supplied to said first plate line; and

a switch control circuit for activating said switch control signal(s) and turning on said switch circuit(s), when said first plate voltage rises to a predetermined voltage after the power turns on.

12. The semiconductor memory according to claim 11, wherein:

each of said inversion circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor;

a source of said pMOS transistor is connected to one of said power source lines through one of said switch circuits;

a source of said nMOS transistor is connected to a ground line, which is the other of said power source lines, through the other of said switch circuits;

a substrate of said pMOS transistor is connected to said power source line; and

a substrate of said nMOS transistor is connected to said ground line.

13. The semiconductor memory according to claim 11, wherein

said switch circuit(s) is/are formed to be common to said plurality of memory cells.

14. A semiconductor memory comprising:

a plurality of memory cells, each of which has

a latch circuit having two inversion circuits whose inputs and outputs are connected to each other,

a pair of first ferroelectric capacitors being connected in series between a first plate line and a second plate line, wherein an intermediate node connecting the pair of first ferroelectric capacitors is connected to an input of one of said inversion circuits, and

a pair of second ferroelectric capacitors being connected in series between said first plate line and said second plate line, wherein an intermediate node connecting the pair of second ferroelectric capacitors is connected to an input of the other of said inversion circuits;

switch circuit(s) for connecting power supply terminals of said inversion circuits to power source line(s) according to switch control signal(s);

a first plate voltage generator for generating a first plate voltage to be supplied to said first plate line;

a second plate voltage generator for generating a second plate voltage which is lower than said first plate voltage and is supplied to said second plate line for a predetermined period after the power turns on; and

a switch control circuit for activating said switch control signal(s) and turning on said switch circuit(s), when said first plate voltage rises to a predetermined voltage after the power turns on.

15. The semiconductor memory according to claim 14, wherein

said second plate voltage generator outputs a ground voltage as said second plate voltage for at least said predetermined period.

16. The semiconductor memory according to claim 14, wherein

each of said inversion circuits is structured of a CMOS inverter made up of a pMOS transistor and an nMOS transistor;

a source of said pMOS transistor is connected to one of said power source lines through one of said switch circuits;

a source of said nMOS transistor is connected to a ground line, which is the other of said power source lines, through the other of said switch circuits;

a substrate of said pMOS transistor is connected to said power source line; and

a substrate of said nMOS transistor is connected to said ground line.

17. The semiconductor memory according to claim 14, wherein said switch circuit(s) is/are formed to be common to said plurality of memory cells.