Apparatus and method for controlling data transmission

• US 20030123389A1
• Filed: 09/20/2002
• Published: 07/03/2003
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Alcatel-Lucent Canada Incorporated (Nokia Corporation)
• Inventors: Russell, Patrick Gene, Chouinard, Luc Alain, Van Asten, Kizito Gysbertus Antonius
• Granted Patent: US 7,751,418 B2
• Time in Patent Office: Days
• US Class Current: 370/230
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Claims

1. An apparatus for controlling the transmission of data, comprising first and second integrated circuit (IC) chips, and data transmission means for transmitting data from said first integrated circuit chip to said second integrated circuit chip,

the first integrated circuit chip having a memory for receiving data for transmission to said second integrated circuit chip, and said second integrated circuit chip having a scheduler and a data output port, said scheduler being arranged to control the transfer of data from said memory to said data output port via the data transmission means.

2. An apparatus as claimed in claim 1, wherein said first IC includes arrival notification means for notifying said scheduler of the arrival of a data packet at said first IC for transmission from said output port.

3. An apparatus as claimed in claim 2, wherein said first IC includes label detection means for detecting a label associated with an incoming data packet, and said arrival notification means is responsive to said label for transmitting an arrival notification to said scheduler.

4. An apparatus as claimed in claim 1, wherein said memory includes a plurality of queues, each for storing data to be transferred to said second IC, and said apparatus further comprises label detection means for detecting labels associated with incoming data, and data storage control means for storing each data in a said queue according to the label associated therewith.

5. An apparatus as claimed in claim 4, wherein said first IC includes arrival notification means for notifying said scheduler of the arrival of data at said first IC for transmission to said second IC, and wherein said notification means is adapted to transmit a notification of the arrival of each data identifying the queue in which said data is stored.

6. An apparatus as claimed in claim 1, wherein said memory includes a plurality of groups of queues, each queue for storing one or more data packets for transmission to said second IC, said apparatus further comprising group notification means adapted to transmit an identification of the group and the queue of that group in which a data packet is stored.

7. An apparatus as claimed in claim 5, wherein said scheduler is arranged to record an indication of the status of each queue based on said arrival notifications.

8. An apparatus as claimed in claim 1, wherein said second IC includes departure request transmission means for transmitting a departure request from said second IC to said first IC identifying a part of said memory from which a data packet is to be output to the second IC, and said data transmission means is responsive to said departure request for transferring data from said identified part of said memory to said second IC.

9. An apparatus as claimed in claim 1, wherein said memory includes a plurality of queues, each for storing data to be transferred to said second IC, said scheduler includes departure request transmitting means for transmitting a departure request from said second IC to said first IC identifying the queue from which a data packet is to be output to said second IC, and said data transmission means is responsive to said departure request for transferring data from said identified queue to said second IC.

10. An apparatus as claimed in claim 9, wherein said memory includes a plurality of groups of queues, and said second IC includes group identity transmission means for transmitting an indication of the group of queues from which the requested data is to be withdrawn, and said data transmission means is responsive to the group identification to transfer data from the identified group of queues.

11. An apparatus as claimed in claim 1, wherein said memory includes a plurality of queues, each for storing data to be transferred to said second IC, and said first IC includes queue status transmission means for transmitting to the scheduler an indication of a status associated with each queue.

12. An apparatus as claimed in claim 11, wherein said queue status transmission means is adapted to transmit to said scheduler a queue status indication when a queue in the memory is empty.

13. An apparatus as claimed in claim 12, wherein said second IC includes correlation means for identifying the queue to which the queue empty status notification relates based on data received from said data transmission means.

14. An apparatus as claimed in claim 1, wherein said data transmission means comprises a data transfer bus and a data transmission controller for outputting data from the memory onto said data transfer bus,

and the apparatus further comprises a control bus for transmitting control signals from the first IC to the second IC.

15. An apparatus as claimed in claim 14, wherein said first IC includes arrival notification means for notifying the scheduler of the arrival of a data packet at the first IC for transmission from said output port, said arrival notification means being adapted to output said arrival notification onto said control bus in a time period of less than or substantially equal to the time period required to output a data packet onto the data transfer bus.

16. An apparatus as claimed in claim 14, wherein said data transmission controller is arranged to output segments of a data packet onto said data transfer bus in a plurality of successive time slots each having a predetermined period.

17. An apparatus as claimed in claim 16, wherein said first IC includes arrival notification means for notifying the scheduler of the arrival of a data packet at said first IC for transmission from said output port,

said arrival notification means being adapted to output an arrival notification onto said control bus in fewer or the same number of time slots having said predetermined period, required for outputting all segments of a data packet onto said data transfer bus.

18. An apparatus as claimed in claim 17, wherein for an arrival notification, said arrival notification means is adapted to transmit on said control bus a first signal in one time slot of a predetermined number of consecutive time slots indicating that a subsequent signal contains information identifying the part of said memory in which the data packet is stored, and to transmit said subsequent signal in a predetermined time slot within said predetermined number of consecutive time slots.

19. An apparatus as claimed in claim 17, wherein said second IC includes data receiving means for receiving data to be transferred to the first IC, and the first IC includes an output port and a scheduler for controlling the transfer of data from said second IC to the output port of said first IC, and departure request transmission means for transmitting to said second IC on said control bus a departure request requesting data from said second IC to said first IC, and wherein said arrival notification means and said departure request transmission means are adapted to output both an arrival notification and a departure request on said control bus in a time period of less than or substantially equal to the time period for outputting a data packet onto the data bus.

20. An apparatus as claimed in claim 19, wherein said data transmission controller is arranged to output segments of a data packet onto said data transfer bus in a plurality of successive time slots, each having a predetermined period,

said arrival notification transmission means is adapted to transmit on said control bus a signal in one time slot of a predetermined number of consecutive time slots indicating that a subsequent signal contains information identifying the part of said memory in which the data packet is stored, and to transmit on said control bus said subsequent signal in a predetermined time slot within said predetermined number of consecutive time slots,

and said departure request transmission means is adapted to transmit on said control bus a signal in one time slot of said predetermined number of consecutive time slots indicating that a subsequent signal contains information identifying the part of said data receiving means in which a requested data packet is stored, and to transmit on said control bus said subsequent signal in a predetermined time slot within said predetermined number of consecutive time slots.

21. An apparatus as claimed in claim 20, wherein said arrival notification means and said departure request transmission means are adapted to transmit said signals indicating a subsequent signal in the same time slot.

22. An apparatus as claimed in claim 21, wherein said first IC includes queue status transmission means adapted to transmit an indication of queue status on said control bus in the same time slot as said arrival notification and departure request signals indicative of a subsequent signal.

23. An apparatus as claimed in claim 21, wherein said first IC further includes error detection means for detecting errors in data packets transmitted from said second IC, and error signal transmission means for transmitting on said control bus and in the same time slot as said arrival notification and departure request signals indicative of a subsequent signal, a signal responsive to the detection of an error.

24. An apparatus as claimed in claim 14, further comprising a second control bus for transmitting control signals from said second IC to said first IC.

25. An apparatus as claimed in claim 24, wherein said second IC further comprises departure request transmission means for transmitting on said second control bus to said first IC a departure request requesting data for transmission from said first IC to said second IC, said departure request transmission means being arranged to output said departure request onto said second control bus in a time period of less than or substantially equal to the time period required to output a data packet onto the data transfer bus.

26. An apparatus as claimed in claim 1, wherein said data transmission means includes a data transfer bus for transmitting data from said IC to said second IC, and said first IC further comprises code transmission means including a code transfer bus, separate from said data transfer bus, and adapted to transmit error detection code associated with a data packet from said first IC to said second IC for enabling errors in said data packet to be detected.

27. An apparatus as claimed in claim 26, wherein said first IC further includes error detection means for detecting errors in incoming data packets based on error detection code associated therewith.

28. An apparatus as claimed in claim 27, wherein said first IC is adapted only to transmit data packets and associated error detection code to said second IC if fewer than a predetermined number of errors in each data packet are detected by said error detection means.

29. An apparatus as claimed in claim 28, wherein said first IC is adapted to transmit a substitute data packet on said data transfer bus and associated error detection code on said code transfer bus in place of a data packet and its associated code in which the number of detected errors exceeds said predetermined number.

30. An apparatus as claimed in claim 26, wherein said code transmission means is adapted to output error detection code on said code transfer bus in a time period of less than or substantially equal to the time period required to output a data packet onto the data transfer bus.

31. An apparatus as claimed in claim 30, wherein said data transmission means includes a data transmission controller arranged to output segments of a data packet onto said data transfer bus in a plurality of successive time slots, each having a predetermined period, and said code transmission means is adapted to output error detection code associated with a data packet in fewer or substantially the same number of time slots having said predetermined period, required to output all segments of an associated data packet.

32. An apparatus as claimed in claim 26, wherein said second IC includes error detection means for detecting errors in data packets transferred from the memory of said first IC to said second IC based on the error detection code associated with each data packet.

33. An apparatus as claimed in claim 32, wherein said second IC includes error notification means for transmitting an error notification to said first IC in response to detecting an error in a data packet transferred from the first IC to the second IC.

34. An apparatus as claimed in claim 33, wherein said first IC includes arrival notification means for notifying said scheduler of the arrival of a data packet at said first IC for transmission from said output port, and wherein said notification means is responsive to said error notification to cease transmission of arrival notifications to said scheduler.

35. An apparatus as claimed in claim 32, wherein said second IC includes departure request transmission means for transmitting a departure request from said second IC to said first IC identifying a part of said memory from which a data packet is to be output to the second IC, said first IC includes data transmission means responsive to said departure request for transferring data from said identified part of said memory onto said data transmission means, and said departure request transmission means is responsive to the detection of errors in said data packets to cease transmission of departure requests to said first IC.

36. An apparatus as claimed in claim 32, wherein said second IC further includes synchronization means for aligning data packets transmitted on said data bus with their respective error detection code transmitted on said code transfer bus and for passing the data packets with their corresponding error detection code to said error detection means, said second IC further including means for transmitting a notification to said first IC in response to detecting an error in data transferred from the first IC to the second IC, and said first IC including synchronization signal transmission means for transmitting a synchronization signal to said synchronization means for the said synchronization means to align said data packets and their respective error correction code.

37. An apparatus as claimed in claim 1, wherein said data transmission means includes a data bus and data transmission interface means for transferring data from said memory onto said data bus, and wherein said data bus comprises a plurality of channels coupled to said interface means, each channel comprising a converter on the said first IC having one or more output ports and a plurality of parallel bus lines for transmitting data from said interface means to said converter, and wherein said converter is adapted to convert a parallel data stream on at least two parallel bus lines to a serial data stream at an output port thereof.

38. An apparatus as claimed in claim 37, wherein each converter is adapted to accelerate the data rate of said serial bit stream relative to the data rate of a single bit line of said parallel bus lines.

39. An apparatus as claimed in claim 38, wherein each converter is adapted to accelerate the data rate of said serial bit stream such that the data rate thereof is substantially equal to the data rate of said parallel data stream.

40. An apparatus as claimed in claim 1, wherein said second IC further includes a memory for receiving data for transmission to said first IC, and said first IC includes a scheduler and a data port, the scheduler of said first IC being arranged to control the transfer of data from the memory of said second IC to the data output port of said first IC.

41. An apparatus as claimed in claim 40, further comprising first control signal transmission means for transmitting an arrival notification from said first IC to the scheduler of said second IC, indicating the arrival of a data packet at said first IC for transmission from the output port of said second IC and for transmitting a departure request from the said first IC to said second IC identifying a part of the memory of said second IC from which a data packet is to be output to said first IC, and second control signal transmission means for transmitting an arrival notification from said second IC to said first IC indicating the arrival of a data packet at said second IC for transmission from the output port of said first IC, and for transmitting a departure request from said second IC to said first IC identifying a part of the memory of said first IC from which a data packet is to be output to the second IC.

42. An apparatus as claimed in claim 1, further comprising one or more further integrated chips and data transmission means for carrying data from the or each further integrated circuit chip to said second integrated circuit chip, wherein the or each further integrated circuit chip has a memory for receiving data for transmission to said second integrated circuit chip, and said scheduler is arranged to control the transfer of data from the memory of the or each further integrated circuit chip to said data output port.

43. An apparatus as claimed in claim 42, wherein the or each further IC includes arrival notification means for notifying said scheduler of the arrival of a data packet at the or each further IC for transmission from said output port.

44. An apparatus as claimed in claim 42, wherein said second IC includes departure request transmission means for transmitting a departure request from said second IC to a selected one of said first IC and the or each further IC identifying a part of the memory of the selected IC from which a data packet is to be output to the second IC, and the or each further IC includes a data transmission controller responsive to said departure request for transferring data from said identified part of said memory onto a respective data transmission means to said second IC.

45. An apparatus as claimed in claim 1, wherein said data transmission means includes a data transfer bus having a plurality of channels, each for transmitting data from said first IC to said second IC, a data transmission controller for transmitting data simultaneously on each of said data channels, said second IC including alignment means for receiving said data from each channel, and outputting said data from each channel simultaneously if the data from at least one channel is received by said alignment means at a different time to the data transmitted on at least one other channel.

46. An apparatus as claimed in claim 45, wherein said first IC includes synchronization signal transmission means for transmitting a synchronization signal-simultaneously on each channel, and said data transmission controller is arranged to transmit data simultaneously on each data channel thereafter, and said alignment means includes detection means for detecting said synchronization signal transmitted on each channel, buffer means for storing data transmitted on each channel, buffer control means adapted to write data received on a respective channel in response to receiving said synchronization signal on that channel, and arranged to output simultaneously from said buffer means the data received on each channel after the data transmitted on all of said channels has been written to said buffer means.

47. A method of transmitting data between a first integrated circuit (IC) and a second integrated circuit (IC) comprising the steps of:

(a) receiving one or more data cells at said first IC for transmission to said second IC,

(b) notifying said second IC of the arrival of the or each data cell,

(c) transmitting a departure request from the second IC to the first IC requesting a data cell,

(d) transmitting a requested data cell from the first IC to the second IC in response to said departure request, and

(e) outputting the requested data cell from the second IC.

48. A method as claimed in claim 47, wherein the step of transmitting a requested data cell comprises transmitting segments of a data cell on a data bus in a plurality of successive time slots.

49. A method as claimed in claim 48, wherein the step of notifying said second IC comprises transmitting an arrival notification on a control bus in fewer or the same number of time slots required to output all segments of a data cell on said data bus.

50. A method as claimed in claim 49, further comprising receiving one or more data cells at said second IC for transmission to said first IC and transmitting said arrival notification and a departure request requesting data from the second IC on said control bus in fewer or substantially the same number of time slots required to transmit all segments of a data cell on said data bus.

51. A method as claimed in claim 50, wherein said arrival notification includes a signal containing information identifying a part of said first IC in which an associated data cell is stored and said departure request includes a signal containing information identifying the part of said second IC in which an associated data cell is stored, and wherein said arrival notification signal and said departure request signal are transmitted on said control bus in different time slots.

52. A method as claimed in claim 51, further comprising, within the same number of time slots required to transmit all segments of a data cell, transmitting control signals in a time slot preceding the time slots used to transmit said arrival notification and departure request signals, wherein one of said control signals indicates that the next arrival notification signal is valid, and another of said control signals indicates that the next departure request signal is valid.

53. A method as claimed in claim 52, further comprising the step of transmitting in said preceding time slot a signal indicating the status of a queue in which a data packet is stored.

54. A method as claimed in claim 53, further comprising transmitting said queue status signal in a time slot which has a predetermined relationship with the time slots in which a data cell is transmitted from the same queue to which the queue status signal relates.

55. A method as claimed in claim 54, further comprising the step of detecting one or more errors in data transmitted on said data bus and transmitting a control signal in said preceding time slot indicative of the occurrence of said one or more errors.

56. A method as claimed in claim 47, wherein the step of transmitting one or more data cells comprises transmitting said one or more data cells on a data bus, and further comprising transmitting on a code transfer bus, separate from said data bus, error detection code associated with the or each data cell for enabling errors in said one or more data cells to be detected.

57. A method as claimed in claim 56, further comprising transmitting error detection code associated with each data cell on said code transfer bus in a time period of less than or substantially equal to the time period required to output a data cell on said data bus.

58. A method as claimed in claim 57, wherein transmitting a data cell comprises transmitting segments of said data cell on said data bus in a plurality of successive time slots, and transmitting error detection code comprises transmitting error detection code associated with said data cell in one or more successive time slots.

59. A method as claimed in claim 47, further comprising transmitting data from a memory of said first IC in a plurality of parallel data streams, converting each of said parallel data streams into a serial data stream having substantially the same data rate as said parallel data stream, transmitting said plurality of serial data streams to said second IC, and converting each of said serial data streams into a parallel data stream at said second IC, said parallel data stream having a data rate which is substantially the same as said serial data stream.

60. A method of initiating data transmission from a first integrated circuit to a second integrated circuit on a plurality of data bus channels, comprising outputting a synchronization signal on each of said channels simultaneously, and thereafter outputting data on each of said channels simultaneously, and, for each channel, receiving said synchronization signal at said second IC, storing data received after said synchronization signal in a buffer,

and outputting simultaneously from the buffers all of the data output simultaneously from the first IC, after all of said data is stored in said buffers.

61. An integrated circuit chip, comprising:

a data input for receiving data from an external source,

a data output for outputting data received at the data input from the chip,

data transfer means for transferring data from the data input to the data output,

a control signal output for outputting control signals from the chip, and

a control signal generator for generating and transmitting control signals to said control signal output for controlling the transfer of data from an external source to said data output via said data input.

62. An integrated circuit chip as claimed in claim 61, wherein said control signal generator includes a scheduler for controlling the order in which data is transferred from said external source to said data input.

63. An integrated circuit chip as claimed in claim 61, further comprising a control signal input for receiving control signals.

64. An integrated circuit chip as claimed in claim 62, further comprising a control signal input, and wherein said scheduler is adapted to record a parameter indicative of the status of a data storage queue of an external source in response to a signal at said control signal input indicating the arrival of data for storage in the queue of said external source.

65. An integrated circuit chip as claimed in claim 61, wherein said control signal generator is adapted to transmit a control signal requesting data from an external source for enabling said external source to transmit the requested data to said data input.

66. An integrated circuit chip as claimed in claim 65, wherein the departure request signal includes an indication of the part of a memory at said external source from which said data is requested.

67. An integrated circuit chip as claimed in claim 66, further comprising a control signal input, and wherein said control signal generator is adapted to cease transmission of signals requesting data from a part of the memory of said external source in response to a control signal at said control signal input indicating that the part of said external memory is empty.

68. An integrated circuit chip as claimed in claim 61, further comprising a code input for receiving code associated with data packets received at said data input for enabling errors in said data packets to be detected, and error detection means for detecting errors in said data packets based on the error detection code associated with each data packet received at code input.

69. An integrated as claimed in claim 68, further comprising error notification means for transmitting a signal indicative of an error from said control signal output in response to said error detection means detecting an error in a data packet received at said data input.

70. An integrated circuit chip as claimed in claim 69, further comprising departure request transmission means for transmitting a departure request from said control signal output requesting data from an external source, said departure request transmission means being responsive to the detection of errors in data packets received at said data input to cease transmission of departure requests.

71. An integrated circuit chip as claimed in claim 68, further comprising synchronization means for aligning data packets received at said data input with their respective error detection code received at said code input and for passing data packets with their corresponding error detection code to said error detection means, said synchronization means being responsive to a synchronization signal transmitted from an external source to align said data packets and their respective error detection code.

72. An integrated circuit chip as claimed in claim 61, wherein said control signal generator is adapted for transmitting from said control signal output, a control signal having a first control function in one time slot and a control signal having a different function in a subsequent time slot.

73. An integrated circuit chip as claimed in claim 72, wherein said control signal generator is adapted for transmitting from said control signal output one or more control signals of a first group of possible control signals in a first time slot and for transmitting from said output a control signal having a different function to the first group of possible control signals in a second time slot.

74. An integrated circuit chip as claimed in claim 61, wherein said control signal generator is adapted for transmitting control signals in time slots of a repeating sequence of a plurality of successive time slots, and is capable of transmitting one or more control signals of a first group of possible control signals in one predetermined time slot of each sequence, and to transmit a control signal having a different function from the first group of control signals in another predetermined time slot of each sequence.

75. An integrated circuit chip as claimed in claim 61, wherein said control signal output comprises a plurality of output ports, and said control signal generator is capable of outputting on an output port in one time slot, a bit of a control signal having a predetermined function, and on said output port in another time slot, a bit of a control signal having a different function.

76. An integrated circuit chip as claimed in claim 75, wherein said control signal generator is adapted to output a control signal in one time slot from said output and a second control signal having a different function in another time slot from said output, wherein said first control signal has a different number of bits than said second control signal.

77. An integrated circuit chip as claimed in claim 61, wherein said control signal output comprises a plurality of output ports, and said control signal generator is adapted to transmit at least one respective control signal of a group of possible control signals on a respective output port, each of said possible control signals having a different function to the other control signals in the group, and to transmit in another time slot, a control signal on at least one of said plurality of output ports having a different function to that of each control signal of said group.

78. An integrated circuit chip as claimed in claim 61, wherein said data input comprises a plurality of data input ports and a transmission system for transmitting data from said input ports to said data output, said data transmission system including a plurality of data channels, each channel including a buffer for temporarily storing data received at an input port, buffer control means responsive to a predetermined signal received at said input port for initiating storage in said buffer of data received at said input port following said predetermined signal, said control means being responsive to an indication that the storage of data has been initiated in the buffers of all of said channels for outputting the first data following said predetermined signal from all of said buffers simultaneously.

79. An integrated circuit chip as claimed in claim 61, further comprising:

a second data input for receiving data from an external source,

a memory for storing said data,

a second data output for outputting data from the chip, and

a control signal input for receiving control signals from an external source for controlling the transfer of data from said memory to said second data output.

80. An integrated circuit chip as claimed in claim 79, further comprising arrival notification means for outputting from said control signal output, a respective signal indicating the arrival of each data at said second data input.

81. An integrated circuit chip as claimed in claim 80, further comprising label detection means for detecting a label associated with incoming data, and wherein said arrival notification signal is indicative of said label.

82. An integrated circuit chip as claimed in claim 79, wherein said memory includes a plurality of queues, each for storing data to be transferred from said chip, and label detection means for detecting labels associated with incoming data, and data storage control means for storing data in said queues according to the label associated therewith.

83. An integrated circuit chip as claimed in claim 82, further including arrival notification means for outputting from said control signal output a respective signal indicating the arrival of each data at said second data input and identifying the queue in which said data is stored.

84. An integrated circuit chip as claimed in claim 79, wherein said memory includes a plurality of queues, each for storing data to be transferred from said chip, and said chip further includes queue status notification means for transmitting a signal from said control signal output indicating a status associated with each queue.

85. An integrated circuit chip as claimed in claim 84, wherein said queue status notification means is adapted to transmit a queue status indication when a queue in said memory is empty.

86. An integrated circuit chip as claimed in claim 79, further comprising a code output for outputting code from the chip and code transmission means adapted to transmit from said code output error detection code associated with a data packet for enabling an error in said data packet to be detected.

87. An integrated circuit chip as claimed in claim 86, further comprising a code memory for storing code associated with each data packet and a memory controller responsive to a signal at said control signal input to output a requested data packet from said memory and the associated code from said code memory.

88. An integrated circuit chip as claimed in claim 86, comprising a memory controller arranged to output a data packet from said memory in a plurality of data packet segments, a respective segment being output in one of a plurality of successive time frames, and wherein said code transmission means is adapted to transmit code associated with each data packet in code segments, each code segment being transmitted to said code output in one of a plurality of successive time frames.

89. An integrated circuit chip as claimed in claim 79, further comprising synchronization signal transmission means for transmitting a synchronization signal from said chip for enabling an external device for receiving data and error correction code from said chip to align said data packets and their respective error correction code, in response to a signal at said control signal input indicative of the occurrence of an error in data packets transmitted from said second data output.

90. An integrated circuit chip as claimed in claim 79, wherein said control signal generator is adapted for transmitting control signals in time slots of a repeating sequence of a plurality of successive time slots, and is capable of transmitting one or more control signals of a first group of possible control signals in one predetermined time slot of each sequence, and to transmit a control signal having a different function from the first group of control signals in another predetermined time slot of each sequence.

91. An integrated circuit chip as claimed in claim 90, wherein the period of each sequence of time slots is less than or equal to the period for transferring a data packet from said memory.

92. An integrated circuit chip as claimed in claim 90, wherein said group of possible control signals includes at least one of:

a signal indicating that a subsequent signal in a predetermined one of that sequence of time slots contains information identifying data,

a signal enabling a location of data to be identified,

a signal indicating the status of a queue in said memory, and

a signal resulting from the detection of an error in data received at said first data input.

93. An integrated circuit chip as claimed in claim 92, wherein said signal indicating the content of a subsequent signal at said control signal output includes at least one of a signal indicating that a subsequent signal in a predetermined time slot within said sequence of time slots identifies the location of said memory in which a data packet received at said second data input is stored, and a signal indicating that a subsequent signal in a predetermined time slot within said sequence of time slots contains information identifying the location of data at an external source for transfer to said first data input.

94. An integrated circuit chip as claimed in claim 93, wherein said control signal output includes a plurality of output ports, and said control signal generator is adapted for outputting each possible control signal of said first group from a different output port.

95. An integrated circuit chip as claimed in claim 93, wherein said control signal generator is capable of transmitting in the same time slot both said signal indicating that a subsequent signal within a predetermined time slot of said sequence of time slots identifies said location of said memory and said signal indicating that a subsequent signal in a predetermined time slot with said predetermined sequence of time slots identifies said location of said external source, and transmitting said signal containing information identifying the location in said memory in a different time slot of a sequence to the time slot used to transmit said signal containing information identifying a location of data at said external source.

96. An integrated circuit chip as claimed in claim 79, wherein said second data output comprises a plurality of data output ports, and said chip further includes a data transmission system for transmitting data to said plurality of output ports and comprising a plurality of data channels, each channel comprising a converter and a plurality of bit lines for carrying data in parallel to said converter, and wherein said converter is adapted to convert a parallel data stream received on said bit lines into a serial bit stream for transmission from said output port.

97. An integrated circuit chip as claimed in claim 96, wherein said converter is adapted to accelerate the data transmission rate of said serial bit stream relative to the rate at which data is transmitted on one of said bit lines.

98. An integrated circuit chip as claimed in claim 97, wherein the data transmission rate of the serial bit stream from said converter is substantially equal to the data rate of said parallel data stream.

99. An integrated circuit chip as claimed in claim 79, wherein said second data output comprises a plurality of data output ports, and said chip further includes a data transmission system for transmitting data to said plurality of output ports, and comprising a plurality of data channels, each channel comprising a first converter, a first plurality of bit lines for carrying data in parallel to said first converter, a second converter, a second plurality of bit lines for carrying data from said first converter to said second converter, wherein said first converter is adapted to convert a first parallel data stream carried on said first plurality of bit lines into a second parallel bit stream for transmission on said second plurality of bit lines to said second converter, wherein said second parallel bit stream is capable of being carried on fewer bit lines than said first parallel data stream and said second converter is adapted to convert said second parallel data stream into a serial bit stream for transmission from said output port.

100. An integrated circuit chip as claimed in claim 99, wherein said first converter is adapted to accelerate the data transmission rate of data output on one of said second plurality of bit lines relative to the rate at which data is transmitted on one of said first plurality of bit lines.

101. An integrated circuit chip as claimed in claim 100, wherein said second converter is adapted to accelerate the transmission rate of said serial bit stream relative to the rate at which data is transmitted on one of said second plurality of bit lines.

102. An integrated circuit chip as claimed in claim 79, further comprising a data transmission controller responsive to a signal at said control signal input for outputting a data packet from said memory in a plurality of data packet segments, wherein a respective segment is output in a respective one of a plurality of successive time slots.

103. An integrated circuit as claimed in claim 102, further comprising a code output for outputting code associated with a data packet for enabling errors in said data packet to be detected, and a code transmission controller responsive to a signal at said control signal input for outputting said error detection code from said code output in a plurality of code segments, wherein a respective code segment is output in a respective one of a plurality of successive time slots.

104. An integrated circuit chip as claimed in claim 102, further comprising a code output for outputting code associated with a data packet for enabling errors in said data packet to be detected, and a code transmission controller responsive to a signal at said control signal input for outputting said error detection code from said code output in a plurality of code segments, wherein a respective code segment is output in a respective one of a plurality of successive time slots, and said code transmission controller is adapted to transmit said code segments in the same or fewer number of time slots required for outputting said data packet.

105. An integrated circuit chip as claimed in claim 102, wherein said control signal generator is adapted to transmit a control signal from said control signal output identifying the part of said memory in which an incoming data packet received at said second data input is stored and/or a control signal identifying a location of data in an external source for transmission to said first data input port within a period of less than or equal to the period required for outputting all segments of a data packet from said memory.

106. An interface for transmitting data from a first circuit to a second circuit, comprising a data bus, transmitting means for transmitting data onto the data bus, and receiving means for receiving data from the data bus, the data bus including a plurality of channels, wherein each channel comprises a plurality of parallel bus lines, a converter for receiving parallel data from the parallel bus lines and converting the parallel data to a serial data stream, wherein the converter is adapted to transmit the serial data stream at a higher rate than the rate at which data is transmitted on one bus line of said plurality of parallel bus lines.

107. An interface as claimed in claim 106, wherein the first converter is arranged to transmit the serial data stream onto said serial bus line at a rate which is substantially equal to or greater than the net rate of transfer of parallel data over said first plurality of parallel bus lines.

108. An interface as claimed in claim 106, wherein each of said channels further comprises a second converter for receiving the serial data stream from the first converter and converting the serial data stream into a parallel data flow, and a second plurality of parallel bus lines for carrying the parallel data from the second converter to said receiving means.

109. An interface as claimed in claim 108, wherein each of said plurality of channels further comprises a third converter, a first group of parallel bus lines for carrying parallel data from said transmitting means to said third converter and a second group of parallel bus lines for carrying parallel data from said third converter to said first converter, and wherein said converter is adapted to convert the parallel data received from said transmitter for transmission on said second group of parallel bus lines, wherein the number of bus lines contained in said second group is less than the number of bus lines contained in said first group.

110. An interface as claimed in claim 106, wherein each of said plurality of channels further comprises a detector for detecting a predetermined pattern transmitted on said channel, a register for receiving data transmitted on said channel, writing means for writing data into said register in response to said detector detecting said pattern, further detection means for detecting when all of said registers contain data and reading means for reading data from each of said registers in response to said further detection means.

111. An interface for transmitting data from a first device to a second device, comprising storage means for storing data and associated code for detecting an error in said data, a first bus for transmitting data stored in said storage means from said first device to said second device, and a second bus for transmitting code stored in said storage means from said first device to said second device.