Method for fabricating semiconductor device capable of covering facet on plug

• US 20030124465A1
• Filed: 11/14/2002
• Published: 07/03/2003
• Est. Priority Date: 12/27/2001
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Min-Suk, Lee, Sung-Kwon, Hwang, Chang-Youn, Suh, Weon-Joon, Kim, Sang-Ik
• Application Number:
  US10/293,497
• Publication Number:
  US 20030124465A1
• Time in Patent Office: Days
• US Class Current: 430/314
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

The present invention relates to a method for fabricating a semiconductor device capable of improving an overlap margin that occurs when forming a conductive pattern, such as a bit line or a bit line contact. In order to achieve this effect, the method for fabricating a semiconductor device includes the steps of: forming a plug passing through an insulation layer to be contacted with a substrate board; forming a planarization insulation layer on an entire surface including the plug so as to cover defects appeared at a surface of the plug; forming a protective insulation layer on the planarization insulation layer for preventing losses of the planarization insulation layer resulted from a subsequent cleaning process; performing a process with an etchant; and forming a conductive layer contacted to the plug by passing through the protective insulation layer and the planarization insulation layer.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of:

forming a plug passing through an insulation layer to be contacted with a substrate;

forming a planarization insulation layer on an entire surface including the plug so as to cover defects appeared at a surface of the plug;

forming a protective insulation layer on the planarization insulation layer for preventing losses of the planarization insulation layer resulted from a subsequent cleaning process;

performing a process with an etchant; and

forming a conductive layer contacted to the plug by passing through the protective insulation layer and the planarization insulation layer.

2. The method as recited in claim 1, wherein the etchant is dilute HF or BOE.

3. The method as recited in claim 2, wherein the dilution of the etchant to the water is from about 100:

1 to about 500;

1.

4. The method as recited in claim 1, wherein the planarization insulation layer includes a flowable insulation layer or a undoped silicate glass (USG) layer that uses SiH₄.

5. The method as recited in claim 4, wherein the flowable insulation layer is An advanced planarization layer.

6. The method as recited in claim 4, wherein the flowable insulation layer is formed with a thickness in a range from about 500 Å

to about 3000 Å

.

7. The method as recited in claim 4, wherein the USG layer that uses SiH₄ is formed with a thickness in a range from about 500 Å

to about 3000 Å

.

8. The method as recited in claim 1, wherein the protective insulation layer includes a high density plasma (HDP) oxide layer or a tetra ethyl ortho silicate (TEOS) layer.

9. The method as recited in claim 8, wherein the HDP oxide layer has a thickness in a range from about 500 Å

to about 3000 Å

.

10. The method as recited in claim 8, wherein the TEOS layer is formed with a thickness in a range from about 500 A to about 3000 Å

.

11. The method as recited in claim 1, wherein the plug is formed through the use of a selective epitaxial growth (SEG).